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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
| commit | 6e09df71a333bf87cd68c2d08ad068a3e501462d (patch) | |
| tree | 7d76e0626e61ef5a9f15c62358337674fb0095aa /miasm2/arch/mips32/regs.py | |
| parent | e8d0fcf8d28d82a8f33138d044f335634ac3a30c (diff) | |
| download | miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.tar.gz miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.zip | |
Modify irbloc destination mecanism. Rework API in consequence.
Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
Diffstat (limited to 'miasm2/arch/mips32/regs.py')
| -rw-r--r-- | miasm2/arch/mips32/regs.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py index ef5e380c..64df4b98 100644 --- a/miasm2/arch/mips32/regs.py +++ b/miasm2/arch/mips32/regs.py @@ -4,6 +4,7 @@ from miasm2.expression.expression import * from miasm2.core.cpu import gen_reg, gen_regs + gen_reg('PC', globals()) gen_reg('PC_FETCH', globals()) |