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authorFabrice Desclaux <fabrice.desclaux@cea.fr>2014-09-05 11:30:05 +0200
committerFabrice Desclaux <fabrice.desclaux@cea.fr>2014-09-05 11:30:05 +0200
commit6e09df71a333bf87cd68c2d08ad068a3e501462d (patch)
tree7d76e0626e61ef5a9f15c62358337674fb0095aa /miasm2/arch/msp430/ira.py
parente8d0fcf8d28d82a8f33138d044f335634ac3a30c (diff)
downloadmiasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.tar.gz
miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.zip
Modify irbloc destination mecanism. Rework API in consequence.
Fat patch here: some API have changed.

Each irbloc now affects a special "IRDst" register which is used to
describe the destination irbloc. It allows simple description of
architectures using delay slots. Architectures semantic and tcc/python
jitter are modified in consequence. LLVM jitter is disabled for now,
but should be patch soon.
Diffstat (limited to 'miasm2/arch/msp430/ira.py')
-rw-r--r--miasm2/arch/msp430/ira.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/miasm2/arch/msp430/ira.py b/miasm2/arch/msp430/ira.py
index 8e9a70dd..ea8bdc2c 100644
--- a/miasm2/arch/msp430/ira.py
+++ b/miasm2/arch/msp430/ira.py
@@ -65,7 +65,8 @@ class ir_a_msp430(ir_a_msp430_base):
             lbl = bloc.get_next()
             new_lbl = self.gen_label()
             irs = self.call_effects(pc_val)
-            nbloc = irbloc(new_lbl, ExprId(lbl, size=self.pc.size), irs)
+            irs.append([ExprAff(IRDst, ExprId(lbl, size=self.pc.size))])
+            nbloc = irbloc(new_lbl, irs)
             nbloc.lines = [l]
             self.blocs[new_lbl] = nbloc
             irb.dst = ExprId(new_lbl, size=self.pc.size)