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authorFabrice Desclaux <fabrice.desclaux@cea.fr>2017-02-14 19:58:57 +0100
committerFabrice Desclaux <fabrice.desclaux@cea.fr>2017-03-13 14:10:35 +0100
commite94fb099ce7cf80f57d21306de4c2b59ce7b3006 (patch)
tree5c3f23edb7451622c21b5bce32b18bc87b2e10df /miasm2/arch/msp430/ira.py
parent73828c4be50c21eae080d0e2150093a8641baab0 (diff)
downloadmiasm-e94fb099ce7cf80f57d21306de4c2b59ce7b3006.tar.gz
miasm-e94fb099ce7cf80f57d21306de4c2b59ce7b3006.zip
Arch: clean ira/jit
Diffstat (limited to 'miasm2/arch/msp430/ira.py')
-rw-r--r--miasm2/arch/msp430/ira.py32
1 files changed, 14 insertions, 18 deletions
diff --git a/miasm2/arch/msp430/ira.py b/miasm2/arch/msp430/ira.py
index 46b0b5c9..0dc63c61 100644
--- a/miasm2/arch/msp430/ira.py
+++ b/miasm2/arch/msp430/ira.py
@@ -1,11 +1,7 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
-from miasm2.ir.ir import IRBlock, AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.msp430.sem import ir_msp430
-from miasm2.arch.msp430.regs import *
-# from miasm2.core.graph import DiGraph
 
 
 class ir_a_msp430_base(ir_msp430, ira):
@@ -21,19 +17,19 @@ class ir_a_msp430(ir_a_msp430_base):
         ir_a_msp430_base.__init__(self, symbol_pool)
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.cf)
-
-        b.rw[-1][1].add(self.arch.regs.res)
-        b.rw[-1][1].add(self.arch.regs.scg1)
-        b.rw[-1][1].add(self.arch.regs.scg0)
-        b.rw[-1][1].add(self.arch.regs.osc)
-        b.rw[-1][1].add(self.arch.regs.cpuoff)
-        b.rw[-1][1].add(self.arch.regs.gie)
-
-    def get_out_regs(self, b):
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
+
+        irblock.rw[-1][1].add(self.arch.regs.res)
+        irblock.rw[-1][1].add(self.arch.regs.scg1)
+        irblock.rw[-1][1].add(self.arch.regs.scg0)
+        irblock.rw[-1][1].add(self.arch.regs.osc)
+        irblock.rw[-1][1].add(self.arch.regs.cpuoff)
+        irblock.rw[-1][1].add(self.arch.regs.gie)
+
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])