Merge pull request #497 from serpilliere/rename_symb

Rename symb

1 files changed, 10 insertions, 10 deletions

diff --git a/miasm2/arch/msp430/jit.py b/miasm2/arch/msp430/jit.py
index 95d34f96..dd5fe94e 100644
--- a/miasm2/arch/msp430/jit.py
+++ b/miasm2/arch/msp430/jit.py
@@ -1,6 +1,6 @@
 from miasm2.jitter.jitload import jitter
-from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core import asmblock
+from miasm2.core.utils import pck16, upck16
 from miasm2.arch.msp430.sem import ir_msp430
 
 import logging
@@ -14,27 +14,27 @@ log.setLevel(logging.CRITICAL)
 class jitter_msp430(jitter):
 
     def __init__(self, *args, **kwargs):
-        sp = asmbloc.asm_symbol_pool()
+        sp = asmblock.AsmSymbolPool()
         jitter.__init__(self, ir_msp430(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint16_t(self, v):
+    def push_uint16_t(self, value):
         regs = self.cpu.get_gpreg()
         regs['SP'] -= 2
         self.cpu.set_gpreg(regs)
-        self.vm.set_mem(regs['SP'], pck16(v))
+        self.vm.set_mem(regs['SP'], pck16(value))
 
     def pop_uint16_t(self):
         regs = self.cpu.get_gpreg()
-        x = upck16(self.vm.get_mem(regs['SP'], 2))
+        value = upck16(self.vm.get_mem(regs['SP'], 2))
         regs['SP'] += 2
         self.cpu.set_gpreg(regs)
-        return x
+        return value
 
-    def get_stack_arg(self, n):
+    def get_stack_arg(self, index):
         regs = self.cpu.get_gpreg()
-        x = upck16(self.vm.get_mem(regs['SP'] + 2 * n, 2))
-        return x
+        value = upck16(self.vm.get_mem(regs['SP'] + 2 * index, 2))
+        return value
 
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)