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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2016-07-30 00:12:33 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2016-08-30 11:08:16 +0200 |
| commit | d441330ab409cfb0a8d3e0ebcfccafef54c32cd0 (patch) | |
| tree | b0dda66bbed78a243b6d32ec8760dd69ec5e367a /miasm2/arch/msp430/regs.py | |
| parent | f2a9a353b32bf59a06b8738ab05e1d20109f71c9 (diff) | |
| download | miasm-d441330ab409cfb0a8d3e0ebcfccafef54c32cd0.tar.gz miasm-d441330ab409cfb0a8d3e0ebcfccafef54c32cd0.zip | |
Jitter: code generator rework
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/msp430/regs.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/miasm2/arch/msp430/regs.py b/miasm2/arch/msp430/regs.py index 60638f26..1e35029f 100644 --- a/miasm2/arch/msp430/regs.py +++ b/miasm2/arch/msp430/regs.py @@ -7,6 +7,7 @@ from miasm2.core.cpu import reg_info regs16_str = ["PC", "SP", "SR"] + ["R%d" % i for i in xrange(3, 16)] regs16_expr = [ExprId(x, 16) for x in regs16_str] +exception_flags = ExprId('exception_flags', 32) gpregs = reg_info(regs16_str, regs16_expr) |