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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-02-14 17:46:38 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-03-13 14:10:35 +0100 |
| commit | 73828c4be50c21eae080d0e2150093a8641baab0 (patch) | |
| tree | 023ffea903e9aaddfc24409682cc47ae3d45d88d /miasm2/arch/msp430/sem.py | |
| parent | b9c87b0e9167940fbbadf0f642e07ee9d7a678e5 (diff) | |
| download | miasm-73828c4be50c21eae080d0e2150093a8641baab0.tar.gz miasm-73828c4be50c21eae080d0e2150093a8641baab0.zip | |
IR/ir: rename ir to IntermediateRepresentation
Diffstat (limited to 'miasm2/arch/msp430/sem.py')
| -rw-r--r-- | miasm2/arch/msp430/sem.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py index 4b52361d..e8eb91cc 100644 --- a/miasm2/arch/msp430/sem.py +++ b/miasm2/arch/msp430/sem.py @@ -3,7 +3,7 @@ from miasm2.expression.expression import * from miasm2.arch.msp430.regs import * from miasm2.arch.msp430.arch import mn_msp430 -from miasm2.ir.ir import ir +from miasm2.ir.ir import IntermediateRepresentation # Utils @@ -412,10 +412,10 @@ def ComposeExprAff(dst, src): return e -class ir_msp430(ir): +class ir_msp430(IntermediateRepresentation): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_msp430, None, symbol_pool) + IntermediateRepresentation.__init__(self, mn_msp430, None, symbol_pool) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 16) |