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| author | Camille Mougey <commial@gmail.com> | 2017-01-06 14:36:26 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-01-06 14:36:26 +0100 |
| commit | fd1f440961b24872a5a9c0da19cfc94d1d955386 (patch) | |
| tree | 6556ddfd9a7082b2ad8bb2c72228e3d0ab6fbdea /miasm2/arch/x86/ira.py | |
| parent | c5d47bd8cdb510c78501adae460b35d122042563 (diff) | |
| parent | 58e436386f738b2ce38ad1db8b13fc6e16fe293a (diff) | |
| download | miasm-fd1f440961b24872a5a9c0da19cfc94d1d955386.tar.gz miasm-fd1f440961b24872a5a9c0da19cfc94d1d955386.zip | |
Merge pull request #469 from serpilliere/updt_call_effects_api
Updt call effects api
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/x86/ira.py | 41 |
1 files changed, 9 insertions, 32 deletions
diff --git a/miasm2/arch/x86/ira.py b/miasm2/arch/x86/ira.py index bc09add4..d772d9fc 100644 --- a/miasm2/arch/x86/ira.py +++ b/miasm2/arch/x86/ira.py @@ -31,37 +31,14 @@ class ir_a_x86_16(ir_x86_16, ira): for b in leaves: self.set_dead_regs(b) - def post_add_bloc(self, bloc, ir_blocs): - ir.post_add_bloc(self, bloc, ir_blocs) - if not bloc.lines: - return - l = bloc.lines[-1] - sub_call_dst = None - if not l.is_subcall(): - return - sub_call_dst = l.args[0] - if expr_is_label(sub_call_dst): - sub_call_dst = sub_call_dst.name - for irb in ir_blocs: - l = irb.lines[-1] - sub_call_dst = None - if not l.is_subcall(): - continue - sub_call_dst = l.args[0] - if expr_is_label(sub_call_dst): - sub_call_dst = sub_call_dst.name - lbl = bloc.get_next() - new_lbl = self.gen_label() - irs = self.call_effects(l.args[0]) - irs.append(AssignBlock([ExprAff(self.IRDst, - ExprId(lbl, size=self.pc.size))])) - - nbloc = irbloc(new_lbl, irs) - nbloc.lines = [l] * len(irs) - self.blocs[new_lbl] = nbloc - irb.dst = ExprId(new_lbl, size=self.pc.size) - return - + def pre_add_instr(self, block, instr, irb_cur, ir_blocks_all, gen_pc_update): + if not instr.is_subcall(): + return irb_cur + call_effects = self.call_effects(instr.args[0], instr) + for assignblk in call_effects: + irb_cur.irs.append(assignblk) + irb_cur.lines.append(instr) + return None class ir_a_x86_32(ir_x86_32, ir_a_x86_16): @@ -91,7 +68,7 @@ class ir_a_x86_64(ir_x86_64, ir_a_x86_16): ir_x86_64.__init__(self, symbol_pool) self.ret_reg = self.arch.regs.RAX - def call_effects(self, ad): + def call_effects(self, ad, instr): return [AssignBlock([ExprAff(self.ret_reg, ExprOp('call_func_ret', ad, self.sp, self.arch.regs.RCX, |