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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
| commit | 6e09df71a333bf87cd68c2d08ad068a3e501462d (patch) | |
| tree | 7d76e0626e61ef5a9f15c62358337674fb0095aa /miasm2/arch/x86/ira.py | |
| parent | e8d0fcf8d28d82a8f33138d044f335634ac3a30c (diff) | |
| download | miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.tar.gz miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.zip | |
Modify irbloc destination mecanism. Rework API in consequence.
Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
Diffstat (limited to 'miasm2/arch/x86/ira.py')
| -rw-r--r-- | miasm2/arch/x86/ira.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/miasm2/arch/x86/ira.py b/miasm2/arch/x86/ira.py index c7dfb2ac..bf07e7c2 100644 --- a/miasm2/arch/x86/ira.py +++ b/miasm2/arch/x86/ira.py @@ -59,7 +59,9 @@ class ir_a_x86_16(ir_x86_16, ira): lbl = bloc.get_next() new_lbl = self.gen_label() irs = self.call_effects(l.args[0]) - nbloc = irbloc(new_lbl, ExprId(lbl, size=self.pc.size), irs) + irs.append([ExprAff(self.IRDst, ExprId(lbl, size=self.pc.size))]) + + nbloc = irbloc(new_lbl, irs) nbloc.lines = [l] self.blocs[new_lbl] = nbloc b.dst = ExprId(new_lbl, size=self.pc.size) |