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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-10-09 17:04:36 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-10-09 17:04:36 +0200 |
| commit | 7101a6d9d5998102d0dc6a86ac01ba332fed3506 (patch) | |
| tree | 2981aa9d677f614f0ded8476f6e86c20e6c28107 /miasm2/arch/x86/jit.py | |
| parent | 59ef1b1d854cac3e94cd4565a0ac750de9a4c92d (diff) | |
| download | miasm-7101a6d9d5998102d0dc6a86ac01ba332fed3506.tar.gz miasm-7101a6d9d5998102d0dc6a86ac01ba332fed3506.zip | |
Arch/jit: add endianess support jitters
Diffstat (limited to 'miasm2/arch/x86/jit.py')
| -rw-r--r-- | miasm2/arch/x86/jit.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index b1d70f9b..556f70cb 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -17,6 +17,7 @@ class jitter_x86_16(jitter): def __init__(self, *args, **kwargs): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_x86_16(sp), *args, **kwargs) + self.vm.set_little_endian() self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode @@ -48,6 +49,7 @@ class jitter_x86_32(jitter): def __init__(self, *args, **kwargs): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_x86_32(sp), *args, **kwargs) + self.vm.set_little_endian() self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP self.ir_arch.do_stk_segm = False @@ -139,6 +141,7 @@ class jitter_x86_64(jitter): def __init__(self, *args, **kwargs): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_x86_64(sp), *args, **kwargs) + self.vm.set_little_endian() self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP self.ir_arch.do_stk_segm = False |