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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2016-07-30 00:12:33 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2016-08-30 11:08:16 +0200 |
| commit | d441330ab409cfb0a8d3e0ebcfccafef54c32cd0 (patch) | |
| tree | b0dda66bbed78a243b6d32ec8760dd69ec5e367a /miasm2/arch/x86/jit.py | |
| parent | f2a9a353b32bf59a06b8738ab05e1d20109f71c9 (diff) | |
| download | miasm-d441330ab409cfb0a8d3e0ebcfccafef54c32cd0.tar.gz miasm-d441330ab409cfb0a8d3e0ebcfccafef54c32cd0.zip | |
Jitter: code generator rework
Diffstat (limited to 'miasm2/arch/x86/jit.py')
| -rw-r--r-- | miasm2/arch/x86/jit.py | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index c4f6f128..771b651a 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -17,7 +17,6 @@ class jitter_x86_16(jitter): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_x86_16(sp), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode @@ -49,7 +48,6 @@ class jitter_x86_32(jitter): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_x86_32(sp), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode @@ -109,7 +107,6 @@ class jitter_x86_64(jitter): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_x86_64(sp), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode |