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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2019-01-13 21:52:39 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2019-01-13 21:52:39 +0100 |
| commit | fcdc5f9e1f48c284c8626112c802868313afaa2e (patch) | |
| tree | 30a010b762dde9dd3fb8a159770902553a86604e /miasm2/arch/x86/jit.py | |
| parent | 7f12d5bf72e9a236c71845e932c37352c5df642a (diff) | |
| download | miasm-fcdc5f9e1f48c284c8626112c802868313afaa2e.tar.gz miasm-fcdc5f9e1f48c284c8626112c802868313afaa2e.zip | |
Jitter: fix pc update in trace mode
Diffstat (limited to 'miasm2/arch/x86/jit.py')
| -rw-r--r-- | miasm2/arch/x86/jit.py | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index d775cff5..f0a9875e 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -20,16 +20,20 @@ class x86_32_CGen(CGen): self.translator = TranslatorC(self.ir_arch.loc_db) self.init_arch_C() - def gen_post_code(self, attrib): + def gen_post_code(self, attrib, pc_value): out = [] if attrib.log_regs: + # Update PC for dump_gpregs + out.append("%s = %s;" % (self.C_PC, pc_value)) out.append('dump_gpregs_32(jitcpu->cpu);') return out class x86_64_CGen(x86_32_CGen): - def gen_post_code(self, attrib): + def gen_post_code(self, attrib, pc_value): out = [] if attrib.log_regs: + # Update PC for dump_gpregs + out.append("%s = %s;" % (self.C_PC, pc_value)) out.append('dump_gpregs_64(jitcpu->cpu);') return out |