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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-11-07 19:54:36 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-11-07 19:54:36 +0100 |
| commit | 8d095672e048af882102518597217c4eca618afa (patch) | |
| tree | 530e032c911256f430166ecdfe0bf78ab9d021a4 /miasm2/arch/x86/sem.py | |
| parent | 3bdad0fb8c2d4d2603aad1c689f106aaabb54efb (diff) | |
| download | miasm-8d095672e048af882102518597217c4eca618afa.tar.gz miasm-8d095672e048af882102518597217c4eca618afa.zip | |
x86: fix rep ecx
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/x86/sem.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 5d564fb1..81da8107 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -4648,7 +4648,9 @@ class ir_x86_16(IntermediateRepresentation): # get instruction size s = {"B": 8, "W": 16, "D": 32, 'Q': 64}[instr.name[-1]] size = instr.v_opmode() - c_reg = mRCX[instr.mode][:size] + admode = instr.v_admode() + c_reg = mRCX[instr.mode][:admode] + out_ir = [] zf_val = None # set if zf is tested (cmps, scas) |