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authorFabrice Desclaux <fabrice.desclaux@cea.fr>2019-01-15 08:13:09 +0100
committerFabrice Desclaux <fabrice.desclaux@cea.fr>2019-01-15 08:13:09 +0100
commite8a12bea1445afd764f4ef7075075a773fe84677 (patch)
tree4cbe00760c2b888255e273d3ce7adbf1b0599918 /miasm2/arch/x86/sem.py
parent056ef4cd26c98cd8b9c121f2a791c01c5a7052a8 (diff)
downloadmiasm-e8a12bea1445afd764f4ef7075075a773fe84677.tar.gz
miasm-e8a12bea1445afd764f4ef7075075a773fe84677.zip
Rename idiv/imod into sdiv/smod
Diffstat (limited to '')
-rw-r--r--miasm2/arch/x86/sem.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index 244aff30..e01adcbc 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -1754,8 +1754,8 @@ def idiv(ir, instr, src1):
     else:
         raise ValueError('div arg not impl', src1)
 
-    c_d = m2_expr.ExprOp('idiv', src2, src1.signExtend(src2.size))
-    c_r = m2_expr.ExprOp('imod', src2, src1.signExtend(src2.size))
+    c_d = m2_expr.ExprOp('sdiv', src2, src1.signExtend(src2.size))
+    c_r = m2_expr.ExprOp('smod', src2, src1.signExtend(src2.size))
 
     # if 8 bit div, only ax is affected
     if size == 8: