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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-04-14 23:04:46 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-04-20 12:36:51 +0200 |
| commit | 4d511eab15845e519e5a8b0d9f742a550768b709 (patch) | |
| tree | 418429f7a3cdedf5efdf074126bc76dbd04f9657 /miasm2/arch/x86/sem.py | |
| parent | a9b3d7f1a9014336b46c6dca20332a6deaccfc6d (diff) | |
| download | miasm-4d511eab15845e519e5a8b0d9f742a550768b709.tar.gz miasm-4d511eab15845e519e5a8b0d9f742a550768b709.zip | |
IRBlock: move lines in AssignBlock
Diffstat (limited to 'miasm2/arch/x86/sem.py')
| -rw-r--r-- | miasm2/arch/x86/sem.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index b0cdc280..0312891b 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -4617,7 +4617,7 @@ class ir_x86_16(IntermediateRepresentation): dst = self.expr_fix_regs_for_mode(dst, mode) src = self.expr_fix_regs_for_mode(src, mode) new_assignblk[dst] = src - irbloc.irs[idx] = AssignBlock(new_assignblk) + irbloc.irs[idx] = AssignBlock(new_assignblk, assignblk.instr) if irbloc.dst is not None: irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst, mode) |