Merge pull request #366 from itsacoderepo/sem_add_ud2

x86 sem: prefetchw, ud2 and lfence added

1 files changed, 17 insertions, 1 deletions

diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index eb067c55..28e42353 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -2555,7 +2555,20 @@ def fcmovnu(ir, instr, arg1, arg2):
 
 def nop(ir, instr, a=None):
     return [], []
-
+    
+def prefetchw(ir, instr, a=None):
+    # see 4-201 on this documentation 
+    # https://www-ssl.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+    return [], []
+    
+def lfence(ir, instr, a=None):
+    # see 3-485 on this documentation 
+    # https://www-ssl.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
+    return [], []
+    
+def ud2(ir, instr, a=None):
+    e = [m2_expr.ExprAff(exception_flags, m2_expr.ExprInt(EXCEPT_ILLEGAL_INSN, exception_flags.size))]
+    return e, []
 
 def hlt(ir, instr):
     e = []
@@ -4122,6 +4135,9 @@ mnemo_func = {'mov': mov,
               'fcomi': fcomi,
               'fcomip': fcomip,
               'nop': nop,
+              'ud2': ud2,
+              'prefetchw':prefetchw,
+              'lfence':lfence,
               'fnop': nop,  # XXX
               'hlt': hlt,
               'rdtsc': rdtsc,