diff options
| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2019-02-20 14:34:43 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2019-02-20 14:41:08 +0100 |
| commit | c92d002a90f75bfa8b2eaf468d3817647d172641 (patch) | |
| tree | e8a383474318aafc4e6c0fadc322c1f5980cd860 /miasm2/arch/x86/sem.py | |
| parent | 8d3d5b1efb37aae373a9f1d4b50cd17ab79df60c (diff) | |
| download | miasm-c92d002a90f75bfa8b2eaf468d3817647d172641.tar.gz miasm-c92d002a90f75bfa8b2eaf468d3817647d172641.zip | |
X86: makes tsc 64 bit instead of 2 32bits regs
Diffstat (limited to 'miasm2/arch/x86/sem.py')
| -rw-r--r-- | miasm2/arch/x86/sem.py | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index b2ef5a43..d03a7cd4 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -3040,12 +3040,9 @@ def hlt(_, instr): def rdtsc(_, instr): e = [] - e.append(m2_expr.ExprAssign(tsc1, tsc1 + m2_expr.ExprInt(1, 32))) - e.append(m2_expr.ExprAssign(tsc2, tsc2 + m2_expr.ExprCond(tsc1 - tsc1.mask, - m2_expr.ExprInt(0, 32), - m2_expr.ExprInt(1, 32)))) - e.append(m2_expr.ExprAssign(mRAX[32], tsc1)) - e.append(m2_expr.ExprAssign(mRDX[32], tsc2)) + e.append(m2_expr.ExprAssign(tsc, tsc + m2_expr.ExprInt(1, 64))) + e.append(m2_expr.ExprAssign(mRAX[32], tsc[:32])) + e.append(m2_expr.ExprAssign(mRDX[32], tsc[32:])) return e, [] |