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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-02-14 17:46:38 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-03-13 14:10:35 +0100 |
| commit | 73828c4be50c21eae080d0e2150093a8641baab0 (patch) | |
| tree | 023ffea903e9aaddfc24409682cc47ae3d45d88d /miasm2/arch/x86/sem.py | |
| parent | b9c87b0e9167940fbbadf0f642e07ee9d7a678e5 (diff) | |
| download | miasm-73828c4be50c21eae080d0e2150093a8641baab0.tar.gz miasm-73828c4be50c21eae080d0e2150093a8641baab0.zip | |
IR/ir: rename ir to IntermediateRepresentation
Diffstat (limited to 'miasm2/arch/x86/sem.py')
| -rw-r--r-- | miasm2/arch/x86/sem.py | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 50faf557..24b9487a 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -21,7 +21,7 @@ from miasm2.expression.simplifications import expr_simp from miasm2.arch.x86.regs import * from miasm2.arch.x86.arch import mn_x86, repeat_mn, replace_regs from miasm2.expression.expression_helper import expr_cmps, expr_cmpu -from miasm2.ir.ir import ir, IRBlock +from miasm2.ir.ir import IntermediateRepresentation, IRBlock from miasm2.core.sembuilder import SemBuilder import math import struct @@ -4484,10 +4484,10 @@ mnemo_func = {'mov': mov, } -class ir_x86_16(ir): +class ir_x86_16(IntermediateRepresentation): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_x86, 16, symbol_pool) + IntermediateRepresentation.__init__(self, mn_x86, 16, symbol_pool) self.do_stk_segm = False self.do_ds_segm = False self.do_str_segm = False @@ -4622,7 +4622,7 @@ class ir_x86_16(ir): class ir_x86_32(ir_x86_16): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_x86, 32, symbol_pool) + IntermediateRepresentation.__init__(self, mn_x86, 32, symbol_pool) self.do_stk_segm = False self.do_ds_segm = False self.do_str_segm = False @@ -4636,7 +4636,7 @@ class ir_x86_32(ir_x86_16): class ir_x86_64(ir_x86_16): def __init__(self, symbol_pool=None): - ir.__init__(self, mn_x86, 64, symbol_pool) + IntermediateRepresentation.__init__(self, mn_x86, 64, symbol_pool) self.do_stk_segm = False self.do_ds_segm = False self.do_str_segm = False |