Merge pull request #408 from serpilliere/clean_jitter_codegen

Clean jitter codegen

9 files changed, 101 insertions, 16 deletions

diff --git a/miasm2/arch/aarch64/jit.py b/miasm2/arch/aarch64/jit.py
index 44b0609f..ca8d7b39 100644
--- a/miasm2/arch/aarch64/jit.py
+++ b/miasm2/arch/aarch64/jit.py
@@ -11,7 +11,6 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
-
 class jitter_aarch64l(jitter):
     max_reg_arg = 8
 
@@ -19,7 +18,6 @@ class jitter_aarch64l(jitter):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_aarch64l(sp), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
 
     def push_uint64_t(self, v):
         self.cpu.SP -= 8
@@ -70,4 +68,3 @@ class jitter_aarch64b(jitter_aarch64l):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_aarch64b(sp), *args, **kwargs)
         self.vm.set_big_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py
index b198bc43..02a93dd2 100644
--- a/miasm2/arch/aarch64/sem.py
+++ b/miasm2/arch/aarch64/sem.py
@@ -793,7 +793,8 @@ class ir_aarch64l(ir):
                 dst = self.expr_fix_regs_for_mode(dst)
                 src = self.expr_fix_regs_for_mode(src)
                 assignblk[dst] = src
-        irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst)
+        if irbloc.dst is not None:
+            irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst)
 
     def mod_pc(self, instr, instr_ir, extra_ir):
         "Replace PC by the instruction's offset"
diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py
index a9b93f6b..70d16176 100644
--- a/miasm2/arch/arm/jit.py
+++ b/miasm2/arch/arm/jit.py
@@ -17,7 +17,6 @@ class jitter_arml(jitter):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_arml(sp), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
 
     def push_uint32_t(self, v):
         self.cpu.SP -= 4
@@ -67,4 +66,3 @@ class jitter_armb(jitter_arml):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_armb(sp), *args, **kwargs)
         self.vm.set_big_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
index 93223896..332e8d13 100644
--- a/miasm2/arch/mips32/jit.py
+++ b/miasm2/arch/mips32/jit.py
@@ -1,9 +1,11 @@
+import logging
+
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
 from miasm2.core.utils import *
 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
-
-import logging
+from miasm2.jitter.codegen import CGen
+import miasm2.expression.expression as m2_expr
 
 log = logging.getLogger('jit_mips32')
 hnd = logging.StreamHandler()
@@ -11,13 +13,73 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
+
+class mipsCGen(CGen):
+    CODE_INIT = CGen.CODE_INIT + r"""
+    unsigned int branch_dst_pc;
+    unsigned int branch_dst_irdst;
+    unsigned int branch_dst_set=0;
+    """
+
+    CODE_RETURN_NO_EXCEPTION = r"""
+    %s:
+    if (branch_dst_set) {
+        %s = %s;
+        BlockDst->address = %s;
+    } else {
+        BlockDst->address = %s;
+    }
+    return JIT_RET_NO_EXCEPTION;
+    """
+
+    def __init__(self, ir_arch):
+        super(mipsCGen, self).__init__(ir_arch)
+        self.delay_slot_dst = m2_expr.ExprId("branch_dst_irdst")
+        self.delay_slot_set = m2_expr.ExprId("branch_dst_set")
+
+    def block2assignblks(self, block):
+        irblocks_list = super(mipsCGen, self).block2assignblks(block)
+        for instr, irblocks in zip(block.lines, irblocks_list):
+            if not instr.breakflow():
+                continue
+            for irblock in irblocks:
+                for i, assignblock in enumerate(irblock.irs):
+                    if self.ir_arch.pc not in assignblock:
+                        continue
+                    # Add internal branch destination
+                    assignblock[self.delay_slot_dst] = assignblock[
+                        self.ir_arch.pc]
+                    assignblock[self.delay_slot_set] = m2_expr.ExprInt(1, 32)
+                    # Replace IRDst with next instruction
+                    assignblock[self.ir_arch.IRDst] = m2_expr.ExprId(
+                        self.ir_arch.get_next_instr(instr))
+                    irblock.dst = m2_expr.ExprId(
+                        self.ir_arch.get_next_instr(instr))
+        return irblocks_list
+
+    def gen_finalize(self, block):
+        """
+        Generate the C code for the final block instruction
+        """
+
+        lbl = self.get_block_post_label(block)
+        out = (self.CODE_RETURN_NO_EXCEPTION % (lbl.name,
+                                                self.C_PC,
+                                                m2_expr.ExprId('branch_dst_irdst'),
+                                                m2_expr.ExprId('branch_dst_irdst'),
+                                                self.id_to_c(m2_expr.ExprInt(lbl.offset, 32)))
+               ).split('\n')
+        return out
+
+
 class jitter_mips32l(jitter):
 
+    C_Gen = mipsCGen
+
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_mips32l(sp), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
 
     def push_uint32_t(self, v):
         self.cpu.SP -= 4
@@ -38,8 +100,8 @@ class jitter_mips32l(jitter):
 
 
 class jitter_mips32b(jitter_mips32l):
+
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_mips32b(sp), *args, **kwargs)
         self.vm.set_big_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py
index 6ddcf25b..b64b40d5 100644
--- a/miasm2/arch/mips32/regs.py
+++ b/miasm2/arch/mips32/regs.py
@@ -11,6 +11,8 @@ gen_reg('PC_FETCH', globals())
 gen_reg('R_LO', globals())
 gen_reg('R_HI', globals())
 
+exception_flags = ExprId('exception_flags', 32)
+
 PC_init = ExprId("PC_init")
 PC_FETCH_init = ExprId("PC_FETCH_init")
 
diff --git a/miasm2/arch/msp430/jit.py b/miasm2/arch/msp430/jit.py
index 5a4ff58b..95d34f96 100644
--- a/miasm2/arch/msp430/jit.py
+++ b/miasm2/arch/msp430/jit.py
@@ -1,6 +1,7 @@
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
 from miasm2.core.utils import *
+from miasm2.arch.msp430.sem import ir_msp430
 
 import logging
 
@@ -13,11 +14,9 @@ log.setLevel(logging.CRITICAL)
 class jitter_msp430(jitter):
 
     def __init__(self, *args, **kwargs):
-        from miasm2.arch.msp430.sem import ir_msp430
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_msp430(sp), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
 
     def push_uint16_t(self, v):
         regs = self.cpu.get_gpreg()
diff --git a/miasm2/arch/msp430/regs.py b/miasm2/arch/msp430/regs.py
index 60638f26..1e35029f 100644
--- a/miasm2/arch/msp430/regs.py
+++ b/miasm2/arch/msp430/regs.py
@@ -7,6 +7,7 @@ from miasm2.core.cpu import reg_info
 regs16_str = ["PC", "SP", "SR"] + ["R%d" % i for i in xrange(3, 16)]
 regs16_expr = [ExprId(x, 16) for x in regs16_str]
 
+exception_flags = ExprId('exception_flags', 32)
 
 gpregs = reg_info(regs16_str, regs16_expr)
 
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py
index c4f6f128..2e483f2a 100644
--- a/miasm2/arch/x86/jit.py
+++ b/miasm2/arch/x86/jit.py
@@ -4,6 +4,7 @@ from miasm2.jitter.jitload import jitter, named_arguments
 from miasm2.core import asmbloc
 from miasm2.core.utils import *
 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64
+from miasm2.jitter.codegen import CGen
 
 log = logging.getLogger('jit_x86')
 hnd = logging.StreamHandler()
@@ -11,13 +12,34 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
+
+class x86_32_CGen(CGen):
+    def __init__(self, ir_arch):
+        self.ir_arch = ir_arch
+        self.PC = self.ir_arch.arch.regs.RIP
+        self.init_arch_C()
+
+    def gen_post_code(self, attrib):
+        out = []
+        if attrib.log_regs:
+            out.append('dump_gpregs_32(jitcpu->cpu);')
+        return out
+
+class x86_64_CGen(x86_32_CGen):
+    def gen_post_code(self, attrib):
+        out = []
+        if attrib.log_regs:
+            out.append('dump_gpregs_64(jitcpu->cpu);')
+        return out
+
 class jitter_x86_16(jitter):
 
+    C_Gen = x86_32_CGen
+
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_x86_16(sp), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP
         self.ir_arch.do_stk_segm = False
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
         self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
@@ -45,11 +67,12 @@ class jitter_x86_16(jitter):
 
 class jitter_x86_32(jitter):
 
+    C_Gen = x86_32_CGen
+
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_x86_32(sp), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP
         self.ir_arch.do_stk_segm = False
 
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
@@ -105,11 +128,12 @@ class jitter_x86_32(jitter):
 
 class jitter_x86_64(jitter):
 
+    C_Gen = x86_64_CGen
+
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_x86_64(sp), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP
         self.ir_arch.do_stk_segm = False
 
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index 11da1e8b..cdc98fba 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -4571,7 +4571,8 @@ class ir_x86_16(ir):
                 dst = self.expr_fix_regs_for_mode(dst, mode)
                 src = self.expr_fix_regs_for_mode(src, mode)
                 assignblk[dst] = src
-        irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst, mode)
+        if irbloc.dst is not None:
+            irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst, mode)
 
 
 class ir_x86_32(ir_x86_16):