Merge pull request #828 from serpilliere/fix_lgtm_1

Code cleaning: lgtm.com

11 files changed, 24 insertions, 40 deletions

diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py
index 8cb681f6..15a7bd77 100644
--- a/miasm2/arch/aarch64/arch.py
+++ b/miasm2/arch/aarch64/arch.py
@@ -1,7 +1,6 @@
 #-*- coding:utf-8 -*-
 
 import logging
-import math
 from pyparsing import *
 from miasm2.expression import expression as m2_expr
 from miasm2.core.cpu import *
@@ -277,15 +276,15 @@ class aarch64_arg(m_arg):
                 fixed_size.add(value.name.size)
                 return value.name
             loc_key = loc_db.get_or_create_name_location(value.name)
-            return ExprLoc(loc_key, size_hint)
+            return m2_expr.ExprLoc(loc_key, size_hint)
         if isinstance(value, AstInt):
             assert size_hint is not None
-            return ExprInt(value.value, size_hint)
+            return m2_expr.ExprInt(value.value, size_hint)
         if isinstance(value, AstOp):
             if value.op == "segm":
                 segm = self.asm_ast_to_expr(value.args[0], loc_db)
                 ptr = self.asm_ast_to_expr(value.args[1], loc_db, None, fixed_size)
-                return ExprOp('segm', segm, ptr)
+                return m2_expr.ExprOp('segm', segm, ptr)
 
             args = [self.asm_ast_to_expr(arg, loc_db, None, fixed_size) for arg in value.args]
             if len(fixed_size) == 0:
@@ -298,7 +297,7 @@ class aarch64_arg(m_arg):
             else:
                 raise ValueError("Size conflict")
 
-            return ExprOp(value.op, *args)
+            return m2_expr.ExprOp(value.op, *args)
         return None
 
 
@@ -1420,7 +1419,7 @@ class aarch64_offs_pc(imm_noarg, aarch64_arg):
         v = v & self.lmask
         v = (v << 2)
         v = sign_ext(v, (self.l + 2), 64)
-        self.expr = ExprOp("preinc", PC, m2_expr.ExprInt(v, 64))
+        self.expr = m2_expr.ExprOp("preinc", PC, m2_expr.ExprInt(v, 64))
         return True
 
     def encode(self):
diff --git a/miasm2/arch/aarch64/regs.py b/miasm2/arch/aarch64/regs.py
index 85c8425a..1c693b4c 100644
--- a/miasm2/arch/aarch64/regs.py
+++ b/miasm2/arch/aarch64/regs.py
@@ -1,7 +1,6 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import ExprId, ExprInt, ExprLoc, ExprMem, \
-    ExprSlice, ExprCond, ExprCompose, ExprOp
+from miasm2.expression.expression import ExprId
 from miasm2.core.cpu import gen_reg, gen_regs
 
 exception_flags = ExprId('exception_flags', 32)
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py
index c8077ebf..4247a47f 100644
--- a/miasm2/arch/aarch64/sem.py
+++ b/miasm2/arch/aarch64/sem.py
@@ -1,5 +1,5 @@
 from miasm2.expression.expression import ExprId, ExprInt, ExprLoc, ExprMem, \
-    ExprSlice, ExprCond, ExprCompose, ExprOp, ExprAff
+    ExprCond, ExprCompose, ExprOp, ExprAff
 from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock
 from miasm2.arch.aarch64.arch import mn_aarch64, conds_expr, replace_regs
 from miasm2.arch.aarch64.regs import *
@@ -343,8 +343,6 @@ def cmp(ir, instr, arg1, arg2):
 def cmn(ir, instr, arg1, arg2):
     e = []
     arg2 = extend_arg(arg1, arg2)
-    res = arg1 + arg2
-
 
     e += update_flag_arith_add_zn(arg1, arg2)
     e += update_flag_arith_add_co(arg1, arg2)
@@ -443,8 +441,8 @@ def ccmp(ir, instr, arg1, arg2, arg3, arg4):
     res = arg1 - arg2
     new_nf = nf
     new_zf = update_flag_zf(res)[0].src
-    new_cf = update_flag_sub_cf(arg1, arg2, res).src
-    new_of = update_flag_sub_of(arg1, arg2, res).src
+    new_cf = update_flag_sub_cf(arg1, arg2).src
+    new_of = update_flag_sub_of(arg1, arg2).src
 
     e.append(ExprAff(nf, ExprCond(cond_expr,
                                                     new_nf,
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index e25e4911..67d73592 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -1915,7 +1915,6 @@ class arm_offspc(arm_offs):
         if v > (1 << (self.l - 1)) - 1:
             return False
         return v >> 1
-        return False
 
 
 class arm_off8sppc(arm_imm):
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 4e99e720..7dca6242 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -801,7 +801,6 @@ def st_ld_r(ir, instr, a, a2, b, store=False, size=32, s_ext=False, z_ext=False)
             raise ValueError('unhandled case')
     elif size == 32:
         m = ExprMem(ad, size=size)
-        pass
     elif size == 64:
         assert a2 is not None
         m = ExprMem(ad, size=32)
@@ -1176,11 +1175,6 @@ def bfc(ir, instr, a, b, c):
         e.append(ExprAff(ir.IRDst, r))
     return e, []
 
-def rev(ir, instr, a, b):
-    e = []
-    c = ExprCompose(b[24:32], b[16:24], b[8:16], b[:8])
-    e.append(ExprAff(a, c))
-    return e, []
 
 def pld(ir, instr, a):
     e = []
diff --git a/miasm2/arch/mep/arch.py b/miasm2/arch/mep/arch.py
index a4c7182a..cf4fa96d 100644
--- a/miasm2/arch/mep/arch.py
+++ b/miasm2/arch/mep/arch.py
@@ -3,7 +3,8 @@
 
 from miasm2.core.cpu import *
 from miasm2.core.utils import Disasm_Exception
-from miasm2.expression.expression import *
+from miasm2.expression.expression import Expr, ExprId, ExprInt, ExprLoc, \
+    ExprMem, ExprOp
 from miasm2.core.asm_ast import AstId, AstMem
 
 from miasm2.arch.mep.regs import *
diff --git a/miasm2/arch/mep/regs.py b/miasm2/arch/mep/regs.py
index 9564d026..a515e76a 100644
--- a/miasm2/arch/mep/regs.py
+++ b/miasm2/arch/mep/regs.py
@@ -1,7 +1,7 @@
 # Toshiba MeP-c4 - miasm registers definition
 # Guillaume Valadon <guillaume@valadon.net>
 
-from miasm2.expression.expression import *
+from miasm2.expression.expression import ExprId
 from miasm2.core.cpu import reg_info, gen_reg, gen_regs
 
 # Used by internal miasm exceptions
diff --git a/miasm2/arch/mep/sem.py b/miasm2/arch/mep/sem.py
index 3558de70..e1d4c5fa 100644
--- a/miasm2/arch/mep/sem.py
+++ b/miasm2/arch/mep/sem.py
@@ -505,8 +505,8 @@ def bnez(reg_test, disp8):
     """BNEZ - Branch if the register does not store zero."""
 
     # if(Rn!=0) PC <- PC + SignExt((disp8)7..1||0)
-    dst = disp8 if "-"(reg_test, i32(0)) else ExprLoc(ir.get_next_break_loc_key(instr), 32)
-    take_jmp = ExprInt(1, 32) if "-"(reg_test, i32(0)) else ExprInt(0, 32)
+    dst = disp8 if reg_test else ExprLoc(ir.get_next_break_loc_key(instr), 32)
+    take_jmp = ExprInt(1, 32) if reg_test else ExprInt(0, 32)
     PC = dst
     ir.IRDst = dst
 
@@ -516,8 +516,8 @@ def beqi(reg_test, imm4, disp16):
     """BEQI - Branch if the register stores imm4."""
 
     # if(Rn==ZeroExt(imm4)) PC <- PC +SignExt((disp17)16..1||0)
-    dst = ExprLoc(ir.get_next_break_loc_key(instr), 32) if "-"(reg_test, imm4) else disp16
-    take_jmp = ExprInt(0, 32) if "-"(reg_test, imm4) else ExprInt(1, 32)
+    dst = ExprLoc(ir.get_next_break_loc_key(instr), 32) if (reg_test - imm4) else disp16
+    take_jmp = ExprInt(0, 32) if (reg_test - imm4) else ExprInt(1, 32)
     PC = dst
     ir.IRDst = dst
 
@@ -527,8 +527,8 @@ def bnei(reg_test, imm4, disp16):
     """BNEI - Branch if the register does not store imm4."""
 
     # if(Rn!=ZeroExt(imm4)) PC <- PC+SignExt((disp17)16..1||0)
-    dst = disp16 if "-"(reg_test, imm4) else ExprLoc(ir.get_next_break_loc_key(instr), 32)
-    take_jmp = ExprInt(1, 32) if "-"(reg_test, imm4) else ExprInt(0, 32)
+    dst = disp16 if (reg_test - imm4) else ExprLoc(ir.get_next_break_loc_key(instr), 32)
+    take_jmp = ExprInt(1, 32) if (reg_test - imm4) else ExprInt(0, 32)
     PC = dst
     ir.IRDst = dst
 
@@ -560,8 +560,8 @@ def beq(rn, rm, disp16):
     """BEQ - Branch if the two registers are equal."""
 
     # if(Rn==Rm) PC <- PC +SignExt((disp17)16..1||0)
-    dst = ExprLoc(ir.get_next_break_loc_key(instr), 32) if "-"(rn, rm) else disp16
-    take_jmp = ExprInt(0, 32) if "-"(rn, rm) else ExprInt(1, 32)
+    dst = ExprLoc(ir.get_next_break_loc_key(instr), 32) if (rn - rm) else disp16
+    take_jmp = ExprInt(0, 32) if (rn - rm) else ExprInt(1, 32)
     PC = dst
     ir.IRDst = dst
 
@@ -571,8 +571,8 @@ def bne(rn, rm, disp16):
     """BNE - Branch if the two registers are not equal."""
 
     # if(Rn!=Rm) PC <- PC +SignExt((disp17)16..1||0)
-    dst = disp16 if "-"(rn, rm) else ExprLoc(ir.get_next_break_loc_key(instr), 32)
-    take_jmp = ExprInt(1, 32) if "-"(rn, rm) else ExprInt(0, 32)
+    dst = disp16 if (rn - rm) else ExprLoc(ir.get_next_break_loc_key(instr), 32)
+    take_jmp = ExprInt(1, 32) if (rn - rm) else ExprInt(0, 32)
     PC = dst
     ir.IRDst = dst
 
diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py
index 974644dc..f963737e 100644
--- a/miasm2/arch/mips32/arch.py
+++ b/miasm2/arch/mips32/arch.py
@@ -3,7 +3,7 @@
 import logging
 from collections import defaultdict
 
-from pyparsing import Literal, Group, Optional
+from pyparsing import Literal, Optional
 
 from miasm2.expression.expression import ExprMem, ExprInt, ExprId, ExprOp, ExprLoc
 from miasm2.core.bin_stream import bin_stream
diff --git a/miasm2/arch/ppc/sem.py b/miasm2/arch/ppc/sem.py
index 7f165e96..3c885d12 100644
--- a/miasm2/arch/ppc/sem.py
+++ b/miasm2/arch/ppc/sem.py
@@ -184,7 +184,7 @@ def mn_do_div(ir, instr, rd, ra, rb):
         flags_update += mn_compute_flags(rvalue, over_expr)
 
     return ([ ExprAff(rd, rvalue) ] + flags_update), []
-    
+
 
 def mn_do_eqv(ir, instr, ra, rs, rb):
     rvalue = ~(rs ^ rb)
@@ -225,7 +225,6 @@ def mn_do_load(ir, instr, arg1, arg2, arg3=None):
         return mn_do_lmw(ir, instr, arg1, arg2)
     elif instr.name[1] == 'S':
         raise RuntimeError("LSWI, and LSWX need implementing")
-        pass # XXX
 
     size = {'B': 8, 'H': 16, 'W': 32}[instr.name[1]]
 
@@ -565,7 +564,6 @@ def mn_do_store(ir, instr, arg1, arg2, arg3=None):
 
     if instr.name[2] == 'S':
         raise RuntimeError("STSWI, and STSWX need implementing")
-        pass # XXX
 
     size = {'B': 8, 'H': 16, 'W': 32}[instr.name[2]]
 
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index 8c140d7b..a00b6f7c 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -4995,7 +4995,6 @@ mnemo_func = {'mov': mov,
               'jns': jns,
               'jo': jo,
               'jno': jno,
-              'jecxz': jecxz,
               'loop': loop,
               'loopne': loopne,
               'loope': loope,
@@ -5041,8 +5040,6 @@ mnemo_func = {'mov': mov,
               'fucompp': fucompp,
               'comiss': comiss,
               'comisd': comisd,
-              'fcomi': fcomi,
-              'fcomip': fcomip,
               'nop': nop,
               'ud2': ud2,
               'prefetch0': prefetch0,
@@ -5146,7 +5143,6 @@ mnemo_func = {'mov': mov,
               'xlat': xlat,
               'bt': bt,
               'cpuid': cpuid,
-              'jo': jo,
               'fcom': fcom,
               'ftst': ftst,
               'fxam': fxam,