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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-08 17:02:35 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-09 10:55:39 +0100 |
| commit | eca476334f93f023e57048453eb9ec4ee4fab9d2 (patch) | |
| tree | 08ea36af5f8f7f27222631cdbf0b9f18aa3248cc /miasm2/arch | |
| parent | 47811fe5a56c8071ab5064e1f84ca64389941eec (diff) | |
| download | miasm-eca476334f93f023e57048453eb9ec4ee4fab9d2.tar.gz miasm-eca476334f93f023e57048453eb9ec4ee4fab9d2.zip | |
IRBlock: replace irs by assignblks
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/aarch64/sem.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/mips32/ira.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/mips32/jit.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index d8dc1efa..62a3c21c 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -827,7 +827,7 @@ class ir_aarch64l(IntermediateRepresentation): def irbloc_fix_regs_for_mode(self, irblock, mode=64): irs = [] - for assignblk in irblock.irs: + for assignblk in irblock.assignblks: new_assignblk = dict(assignblk) for dst, src in assignblk.iteritems(): del(new_assignblk[dst]) @@ -870,7 +870,7 @@ class ir_aarch64l(IntermediateRepresentation): new_irblocks = [] for irblock in extra_ir: irs = [] - for assignblk in irblock.irs: + for assignblk in irblock.assignblks: new_dsts = {dst:src for dst, src in assignblk.iteritems() if dst not in regs_to_fix} irs.append(AssignBlock(new_dsts, assignblk.instr)) diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py index f1e21a41..ab242815 100644 --- a/miasm2/arch/mips32/ira.py +++ b/miasm2/arch/mips32/ira.py @@ -21,7 +21,7 @@ class ir_a_mips32l(ir_mips32l, ira): for irb in ir_blocks: pc_val = None lr_val = None - for assignblk in irb.irs: + for assignblk in irb.assignblks: pc_val = assignblk.get(self.arch.regs.PC, pc_val) lr_val = assignblk.get(self.arch.regs.RA, lr_val) diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index 493da595..767393bc 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -42,12 +42,12 @@ class mipsCGen(CGen): irblocks_list = super(mipsCGen, self).block2assignblks(block) for irblocks in irblocks_list: for blk_idx, irblock in enumerate(irblocks): - has_breakflow = any(assignblock.instr.breakflow() for assignblock in irblock.irs) + has_breakflow = any(assignblock.instr.breakflow() for assignblock in irblock.assignblks) if not has_breakflow: continue irs = [] - for assignblock in irblock.irs: + for assignblock in irblock.assignblks: if self.ir_arch.pc not in assignblock: irs.append(AssignBlock(assignments, assignblock.instr)) continue diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index deebba8c..cb2f6a87 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -4793,7 +4793,7 @@ class ir_x86_16(IntermediateRepresentation): def irbloc_fix_regs_for_mode(self, irblock, mode=64): irs = [] - for assignblk in irblock.irs: + for assignblk in irblock.assignblks: new_assignblk = dict(assignblk) for dst, src in assignblk.iteritems(): del new_assignblk[dst] |