Modify irbloc destination mecanism. Rework API in consequence.

Fat patch here: some API have changed.

Each irbloc now affects a special "IRDst" register which is used to
describe the destination irbloc. It allows simple description of
architectures using delay slots. Architectures semantic and tcc/python
jitter are modified in consequence. LLVM jitter is disabled for now,
but should be patch soon.

1 files changed, 1 insertions, 2 deletions

diff --git a/miasm2/core/asmbloc.py b/miasm2/core/asmbloc.py
index fc2edd30..ac317e0b 100644
--- a/miasm2/core/asmbloc.py
+++ b/miasm2/core/asmbloc.py
@@ -800,8 +800,7 @@ def gen_non_free_mapping(group_bloc, dont_erase=[]):
     return non_free_mapping
 
 
-def resolve_symbol(
-    group_bloc, symbol_pool, dont_erase=[], max_offset=0xFFFFFFFF):
+def resolve_symbol(group_bloc, symbol_pool, dont_erase=[], max_offset=0xFFFFFFFF):
     """
     place all asmblocs
     """