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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-04-17 00:16:59 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-04-17 00:16:59 +0200 |
| commit | 5c6fd820844d043d30445e852e1352bb1d0cd481 (patch) | |
| tree | da12c6d37702afa343fd9bc81abdc94008603dcf /miasm2/jitter/codegen.py | |
| parent | e7e2d2991ec817fb77924cb314cfcda80a33fde0 (diff) | |
| download | miasm-5c6fd820844d043d30445e852e1352bb1d0cd481.tar.gz miasm-5c6fd820844d043d30445e852e1352bb1d0cd481.zip | |
Jitter: fix post instr exception
PC must not be reevaluated on post instruction error. (llvm backend not affected)
Diffstat (limited to 'miasm2/jitter/codegen.py')
| -rw-r--r-- | miasm2/jitter/codegen.py | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/miasm2/jitter/codegen.py b/miasm2/jitter/codegen.py index 9d005451..9158aeba 100644 --- a/miasm2/jitter/codegen.py +++ b/miasm2/jitter/codegen.py @@ -65,7 +65,7 @@ class CGen(object): CODE_CPU_EXCEPTION_POST_INSTR = r""" if (CPU_exception_flag) { - %s = %s; + %s = DST_value; BlockDst->address = DST_value; return JIT_RET_EXCEPTION; } @@ -75,7 +75,7 @@ class CGen(object): check_memory_breakpoint(&(jitcpu->pyvm->vm_mngr)); check_invalid_code_blocs(&(jitcpu->pyvm->vm_mngr)); if (VM_exception_flag) { - %s = %s; + %s = DST_value; BlockDst->address = DST_value; return JIT_RET_EXCEPTION; } @@ -296,13 +296,12 @@ class CGen(object): '%s' % ret, '%s' % retb], dst2index - def gen_post_instr_checks(self, attrib, dst): + def gen_post_instr_checks(self, attrib): out = [] - dst = self.dst_to_c(dst) if attrib.mem_read | attrib.mem_write: - out += (self.CODE_VM_EXCEPTION_POST_INSTR % (self.C_PC, dst)).split('\n') + out += (self.CODE_VM_EXCEPTION_POST_INSTR % (self.C_PC)).split('\n') if attrib.set_exception or attrib.op_set_exception: - out += (self.CODE_CPU_EXCEPTION_POST_INSTR % (self.C_PC, dst)).split('\n') + out += (self.CODE_CPU_EXCEPTION_POST_INSTR % (self.C_PC)).split('\n') if attrib.mem_read | attrib.mem_write: out.append("reset_memory_access(&(jitcpu->pyvm->vm_mngr));") @@ -340,12 +339,12 @@ class CGen(object): # (consecutive instructions) lbl = self.ir_arch.symbol_pool.getby_offset_create(dst) out += self.gen_post_code(attrib) - out += self.gen_post_instr_checks(attrib, dst) + out += self.gen_post_instr_checks(attrib) out.append('goto %s;' % lbl.name) else: out += self.gen_post_code(attrib) out.append('BlockDst->address = DST_value;') - out += self.gen_post_instr_checks(attrib, dst) + out += self.gen_post_instr_checks(attrib) out.append('\t\treturn JIT_RET_NO_EXCEPTION;') return out |