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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2016-07-30 00:12:33 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2016-08-30 11:08:16 +0200 |
| commit | d441330ab409cfb0a8d3e0ebcfccafef54c32cd0 (patch) | |
| tree | b0dda66bbed78a243b6d32ec8760dd69ec5e367a /miasm2/jitter/jitload.py | |
| parent | f2a9a353b32bf59a06b8738ab05e1d20109f71c9 (diff) | |
| download | miasm-d441330ab409cfb0a8d3e0ebcfccafef54c32cd0.tar.gz miasm-d441330ab409cfb0a8d3e0ebcfccafef54c32cd0.zip | |
Jitter: code generator rework
Diffstat (limited to 'miasm2/jitter/jitload.py')
| -rw-r--r-- | miasm2/jitter/jitload.py | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/miasm2/jitter/jitload.py b/miasm2/jitter/jitload.py index 2371067d..8943e2c7 100644 --- a/miasm2/jitter/jitload.py +++ b/miasm2/jitter/jitload.py @@ -7,9 +7,9 @@ from collections import Sequence, namedtuple, Iterator from miasm2.jitter.csts import * from miasm2.core.utils import * from miasm2.core.bin_stream import bin_stream_vm -from miasm2.ir.ir2C import init_arch_C from miasm2.core.interval import interval from miasm2.jitter.emulatedsymbexec import EmulatedSymbExec +from miasm2.jitter.codegen import CGen hnd = logging.StreamHandler() hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s")) @@ -161,11 +161,14 @@ class jitter: "Main class for JIT handling" + C_Gen = CGen + def __init__(self, ir_arch, jit_type="tcc"): """Init an instance of jitter. @ir_arch: ir instance for this architecture @jit_type: JiT backend to use. Available options are: - "tcc" + - "gcc" - "llvm" - "python" """ @@ -194,7 +197,6 @@ class jitter: self.cpu = jcore.JitCpu() self.ir_arch = ir_arch self.bs = bin_stream_vm(self.vm) - init_arch_C(self.arch) self.symbexec = EmulatedSymbExec(self.cpu, self.ir_arch, {}) self.symbexec.reset_regs() @@ -214,6 +216,8 @@ class jitter: raise RuntimeError('Unsupported jitter: %s' % jit_type) self.jit = JitCore(self.ir_arch, self.bs) + if jit_type in ['tcc', 'gcc']: + self.jit.init_codegen(self.C_Gen(self.ir_arch)) self.cpu.init_regs() self.vm.init_memory_page_pool() |