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| author | Camille Mougey <commial@gmail.com> | 2018-08-06 22:26:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-06 22:26:36 +0200 |
| commit | e38b5dd91d10ad66d537675e4592f68eda9fcce2 (patch) | |
| tree | 912333c96758461e9c226d8da037c0084d3c10a0 /miasm2/jitter | |
| parent | e4a255d9c6175b5d9f2ab15471d848705fe1cc4e (diff) | |
| parent | efc5ec2e8c394475e3a2be68bc29821e4d980b1b (diff) | |
| download | miasm-e38b5dd91d10ad66d537675e4592f68eda9fcce2.tar.gz miasm-e38b5dd91d10ad66d537675e4592f68eda9fcce2.zip | |
Merge pull request #816 from serpilliere/operator_high_level
Operator high level
Diffstat (limited to '')
| -rw-r--r-- | miasm2/jitter/codegen.py | 8 | ||||
| -rw-r--r-- | miasm2/jitter/jitcore_python.py | 7 | ||||
| -rw-r--r-- | miasm2/jitter/llvmconvert.py | 22 |
3 files changed, 33 insertions, 4 deletions
diff --git a/miasm2/jitter/codegen.py b/miasm2/jitter/codegen.py index abba9843..69e83de5 100644 --- a/miasm2/jitter/codegen.py +++ b/miasm2/jitter/codegen.py @@ -8,6 +8,7 @@ from miasm2.ir.ir import IRBlock, AssignBlock from miasm2.ir.translators.C import TranslatorC, int_size_to_bn from miasm2.core.asmblock import AsmBlockBad +from miasm2.expression.simplifications import expr_simp_high_to_explicit TRANSLATOR_NO_SYMBOL = TranslatorC(loc_db=None) @@ -166,6 +167,13 @@ class CGen(object): irblock_head = self.assignblk_to_irbloc(instr, assignblk_head) irblocks = [irblock_head] + assignblks_extra + # Simplify high level operators + out = [] + for irblock in irblocks: + new_irblock = irblock.simplify(expr_simp_high_to_explicit)[1] + out.append(new_irblock) + irblocks = out + for irblock in irblocks: assert irblock.dst is not None irblocks_list.append(irblocks) diff --git a/miasm2/jitter/jitcore_python.py b/miasm2/jitter/jitcore_python.py index 61bd98d0..b97727cd 100644 --- a/miasm2/jitter/jitcore_python.py +++ b/miasm2/jitter/jitcore_python.py @@ -1,7 +1,7 @@ import miasm2.jitter.jitcore as jitcore import miasm2.expression.expression as m2_expr import miasm2.jitter.csts as csts -from miasm2.expression.simplifications import ExpressionSimplifier +from miasm2.expression.simplifications import ExpressionSimplifier, expr_simp_explicit from miasm2.jitter.emulatedsymbexec import EmulatedSymbExec ################################################################################ @@ -20,12 +20,11 @@ class JitCore_Python(jitcore.JitCore): self.ircfg = self.ir_arch.new_ircfg() # CPU & VM (None for now) will be set later - expr_simp = ExpressionSimplifier() - expr_simp.enable_passes(ExpressionSimplifier.PASS_COMMONS) + self.symbexec = self.SymbExecClass( None, None, self.ir_arch, {}, - sb_expr_simp=expr_simp + sb_expr_simp=expr_simp_explicit ) self.symbexec.enable_emulated_simplifications() diff --git a/miasm2/jitter/llvmconvert.py b/miasm2/jitter/llvmconvert.py index 4a0eae93..de5f19df 100644 --- a/miasm2/jitter/llvmconvert.py +++ b/miasm2/jitter/llvmconvert.py @@ -830,6 +830,28 @@ class LLVMFunction(): self.update_cache(expr, ret) return ret + + if op.startswith('zeroExt_'): + arg = expr.args[0] + if expr.size == arg.size: + return arg + new_expr = ExprCompose(arg, ExprInt(0, expr.size - arg.size)) + return self.add_ir(new_expr) + + if op.startswith("signExt_"): + arg = expr.args[0] + add_size = expr.size - arg.size + new_expr = ExprCompose( + arg, + ExprCond( + arg.msb(), + ExprInt(size2mask(add_size), add_size), + ExprInt(0, add_size) + ) + ) + return self.add_ir(new_expr) + + if op == "segm": fc_ptr = self.mod.get_global("segm2addr") |