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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-02 14:04:04 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-02 14:08:22 +0100 |
| commit | ef4bb726154228081a377607698d4293185c72a4 (patch) | |
| tree | 6b3f3a6e5a1499804677800b3959bdc773e66bc7 /miasm2/jitter | |
| parent | 0a2934e0a0744bffa300a6e8954f95defee255be (diff) | |
| download | miasm-ef4bb726154228081a377607698d4293185c72a4.tar.gz miasm-ef4bb726154228081a377607698d4293185c72a4.zip | |
X86: fix cdq/cbw...
Diffstat (limited to 'miasm2/jitter')
| -rw-r--r-- | miasm2/jitter/arch/JitCore_x86.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/miasm2/jitter/arch/JitCore_x86.c b/miasm2/jitter/arch/JitCore_x86.c index 3198eff3..407a01c7 100644 --- a/miasm2/jitter/arch/JitCore_x86.c +++ b/miasm2/jitter/arch/JitCore_x86.c @@ -178,6 +178,29 @@ PyObject * cpu_init_regs(JitCpu* self) } +void dump_gpregs_16(vm_cpu_t* vmcpu) +{ + + printf("EAX %.8"PRIX32" EBX %.8"PRIX32" ECX %.8"PRIX32" EDX %.8"PRIX32" ", + (uint32_t)(vmcpu->RAX & 0xFFFFFFFF), + (uint32_t)(vmcpu->RBX & 0xFFFFFFFF), + (uint32_t)(vmcpu->RCX & 0xFFFFFFFF), + (uint32_t)(vmcpu->RDX & 0xFFFFFFFF)); + printf("ESI %.8"PRIX32" EDI %.8"PRIX32" ESP %.8"PRIX32" EBP %.8"PRIX32" ", + (uint32_t)(vmcpu->RSI & 0xFFFFFFFF), + (uint32_t)(vmcpu->RDI & 0xFFFFFFFF), + (uint32_t)(vmcpu->RSP & 0xFFFFFFFF), + (uint32_t)(vmcpu->RBP & 0xFFFFFFFF)); + printf("EIP %.8"PRIX32" ", + (uint32_t)(vmcpu->RIP & 0xFFFFFFFF)); + printf("zf %.1"PRIX32" nf %.1"PRIX32" of %.1"PRIX32" cf %.1"PRIX32"\n", + (uint32_t)(vmcpu->zf & 0x1), + (uint32_t)(vmcpu->nf & 0x1), + (uint32_t)(vmcpu->of & 0x1), + (uint32_t)(vmcpu->cf & 0x1)); + +} + void dump_gpregs_32(vm_cpu_t* vmcpu) { |