Convert to src-layout ta/nix

1 files changed, 192 insertions, 0 deletions

diff --git a/src/miasm/jitter/arch/JitCore_ppc32_regs.h b/src/miasm/jitter/arch/JitCore_ppc32_regs.h
new file mode 100644
index 00000000..79191d32
--- /dev/null
+++ b/src/miasm/jitter/arch/JitCore_ppc32_regs.h
@@ -0,0 +1,192 @@
+JITCORE_PPC_REG_EXPAND(R0, 32)
+JITCORE_PPC_REG_EXPAND(R1, 32)
+JITCORE_PPC_REG_EXPAND(R2, 32)
+JITCORE_PPC_REG_EXPAND(R3, 32)
+JITCORE_PPC_REG_EXPAND(R4, 32)
+JITCORE_PPC_REG_EXPAND(R5, 32)
+JITCORE_PPC_REG_EXPAND(R6, 32)
+JITCORE_PPC_REG_EXPAND(R7, 32)
+JITCORE_PPC_REG_EXPAND(R8, 32)
+JITCORE_PPC_REG_EXPAND(R9, 32)
+JITCORE_PPC_REG_EXPAND(R10, 32)
+JITCORE_PPC_REG_EXPAND(R11, 32)
+JITCORE_PPC_REG_EXPAND(R12, 32)
+JITCORE_PPC_REG_EXPAND(R13, 32)
+JITCORE_PPC_REG_EXPAND(R14, 32)
+JITCORE_PPC_REG_EXPAND(R15, 32)
+JITCORE_PPC_REG_EXPAND(R16, 32)
+JITCORE_PPC_REG_EXPAND(R17, 32)
+JITCORE_PPC_REG_EXPAND(R18, 32)
+JITCORE_PPC_REG_EXPAND(R19, 32)
+JITCORE_PPC_REG_EXPAND(R20, 32)
+JITCORE_PPC_REG_EXPAND(R21, 32)
+JITCORE_PPC_REG_EXPAND(R22, 32)
+JITCORE_PPC_REG_EXPAND(R23, 32)
+JITCORE_PPC_REG_EXPAND(R24, 32)
+JITCORE_PPC_REG_EXPAND(R25, 32)
+JITCORE_PPC_REG_EXPAND(R26, 32)
+JITCORE_PPC_REG_EXPAND(R27, 32)
+JITCORE_PPC_REG_EXPAND(R28, 32)
+JITCORE_PPC_REG_EXPAND(R29, 32)
+JITCORE_PPC_REG_EXPAND(R30, 32)
+JITCORE_PPC_REG_EXPAND(R31, 32)
+
+JITCORE_PPC_REG_EXPAND(PC, 32)
+JITCORE_PPC_REG_EXPAND(LR, 32)
+JITCORE_PPC_REG_EXPAND(CTR, 32)
+JITCORE_PPC_REG_EXPAND(MSR, 32)
+
+JITCORE_PPC_REG_EXPAND(XER_SO, 32)
+JITCORE_PPC_REG_EXPAND(XER_OV, 32)
+JITCORE_PPC_REG_EXPAND(XER_CA, 32)
+JITCORE_PPC_REG_EXPAND(XER_BC, 32)
+
+JITCORE_PPC_REG_EXPAND(CR0_LT, 8)
+JITCORE_PPC_REG_EXPAND(CR0_GT, 8)
+JITCORE_PPC_REG_EXPAND(CR0_EQ, 8)
+JITCORE_PPC_REG_EXPAND(CR0_SO, 8)
+JITCORE_PPC_REG_EXPAND(CR1_LT, 8)
+JITCORE_PPC_REG_EXPAND(CR1_GT, 8)
+JITCORE_PPC_REG_EXPAND(CR1_EQ, 8)
+JITCORE_PPC_REG_EXPAND(CR1_SO, 8)
+JITCORE_PPC_REG_EXPAND(CR2_LT, 8)
+JITCORE_PPC_REG_EXPAND(CR2_GT, 8)
+JITCORE_PPC_REG_EXPAND(CR2_EQ, 8)
+JITCORE_PPC_REG_EXPAND(CR2_SO, 8)
+JITCORE_PPC_REG_EXPAND(CR3_LT, 8)
+JITCORE_PPC_REG_EXPAND(CR3_GT, 8)
+JITCORE_PPC_REG_EXPAND(CR3_EQ, 8)
+JITCORE_PPC_REG_EXPAND(CR3_SO, 8)
+JITCORE_PPC_REG_EXPAND(CR4_LT, 8)
+JITCORE_PPC_REG_EXPAND(CR4_GT, 8)
+JITCORE_PPC_REG_EXPAND(CR4_EQ, 8)
+JITCORE_PPC_REG_EXPAND(CR4_SO, 8)
+JITCORE_PPC_REG_EXPAND(CR5_LT, 8)
+JITCORE_PPC_REG_EXPAND(CR5_GT, 8)
+JITCORE_PPC_REG_EXPAND(CR5_EQ, 8)
+JITCORE_PPC_REG_EXPAND(CR5_SO, 8)
+JITCORE_PPC_REG_EXPAND(CR6_LT, 8)
+JITCORE_PPC_REG_EXPAND(CR6_GT, 8)
+JITCORE_PPC_REG_EXPAND(CR6_EQ, 8)
+JITCORE_PPC_REG_EXPAND(CR6_SO, 8)
+JITCORE_PPC_REG_EXPAND(CR7_LT, 8)
+JITCORE_PPC_REG_EXPAND(CR7_GT, 8)
+JITCORE_PPC_REG_EXPAND(CR7_EQ, 8)
+JITCORE_PPC_REG_EXPAND(CR7_SO, 8)
+
+JITCORE_PPC_REG_EXPAND(SPRG0, 32)
+JITCORE_PPC_REG_EXPAND(SPRG1, 32)
+JITCORE_PPC_REG_EXPAND(SPRG2, 32)
+JITCORE_PPC_REG_EXPAND(SPRG3, 32)
+JITCORE_PPC_REG_EXPAND(SRR0, 32)
+JITCORE_PPC_REG_EXPAND(SRR1, 32)
+JITCORE_PPC_REG_EXPAND(DAR, 32)
+JITCORE_PPC_REG_EXPAND(DSISR, 32)
+JITCORE_PPC_REG_EXPAND(PIR, 32)
+JITCORE_PPC_REG_EXPAND(PVR, 32)
+JITCORE_PPC_REG_EXPAND(DEC, 32)
+JITCORE_PPC_REG_EXPAND(TBL, 32)
+JITCORE_PPC_REG_EXPAND(TBU, 32)
+
+JITCORE_PPC_REG_EXPAND(SR0, 32)
+JITCORE_PPC_REG_EXPAND(SR1, 32)
+JITCORE_PPC_REG_EXPAND(SR2, 32)
+JITCORE_PPC_REG_EXPAND(SR3, 32)
+JITCORE_PPC_REG_EXPAND(SR4, 32)
+JITCORE_PPC_REG_EXPAND(SR5, 32)
+JITCORE_PPC_REG_EXPAND(SR6, 32)
+JITCORE_PPC_REG_EXPAND(SR7, 32)
+JITCORE_PPC_REG_EXPAND(SR8, 32)
+JITCORE_PPC_REG_EXPAND(SR9, 32)
+JITCORE_PPC_REG_EXPAND(SR10, 32)
+JITCORE_PPC_REG_EXPAND(SR11, 32)
+JITCORE_PPC_REG_EXPAND(SR12, 32)
+JITCORE_PPC_REG_EXPAND(SR13, 32)
+JITCORE_PPC_REG_EXPAND(SR14, 32)
+JITCORE_PPC_REG_EXPAND(SR15, 32)
+JITCORE_PPC_REG_EXPAND(IBAT0U, 32)
+JITCORE_PPC_REG_EXPAND(IBAT0L, 32)
+JITCORE_PPC_REG_EXPAND(IBAT1U, 32)
+JITCORE_PPC_REG_EXPAND(IBAT1L, 32)
+JITCORE_PPC_REG_EXPAND(IBAT2U, 32)
+JITCORE_PPC_REG_EXPAND(IBAT2L, 32)
+JITCORE_PPC_REG_EXPAND(IBAT3U, 32)
+JITCORE_PPC_REG_EXPAND(IBAT3L, 32)
+JITCORE_PPC_REG_EXPAND(DBAT0U, 32)
+JITCORE_PPC_REG_EXPAND(DBAT0L, 32)
+JITCORE_PPC_REG_EXPAND(DBAT1U, 32)
+JITCORE_PPC_REG_EXPAND(DBAT1L, 32)
+JITCORE_PPC_REG_EXPAND(DBAT2U, 32)
+JITCORE_PPC_REG_EXPAND(DBAT2L, 32)
+JITCORE_PPC_REG_EXPAND(DBAT3U, 32)
+JITCORE_PPC_REG_EXPAND(DBAT3L, 32)
+JITCORE_PPC_REG_EXPAND(SDR1, 32)
+
+JITCORE_PPC_REG_EXPAND(FPR0, 64)
+JITCORE_PPC_REG_EXPAND(FPR1, 64)
+JITCORE_PPC_REG_EXPAND(FPR2, 64)
+JITCORE_PPC_REG_EXPAND(FPR3, 64)
+JITCORE_PPC_REG_EXPAND(FPR4, 64)
+JITCORE_PPC_REG_EXPAND(FPR5, 64)
+JITCORE_PPC_REG_EXPAND(FPR6, 64)
+JITCORE_PPC_REG_EXPAND(FPR7, 64)
+JITCORE_PPC_REG_EXPAND(FPR8, 64)
+JITCORE_PPC_REG_EXPAND(FPR9, 64)
+JITCORE_PPC_REG_EXPAND(FPR10, 64)
+JITCORE_PPC_REG_EXPAND(FPR11, 64)
+JITCORE_PPC_REG_EXPAND(FPR12, 64)
+JITCORE_PPC_REG_EXPAND(FPR13, 64)
+JITCORE_PPC_REG_EXPAND(FPR14, 64)
+JITCORE_PPC_REG_EXPAND(FPR15, 64)
+JITCORE_PPC_REG_EXPAND(FPR16, 64)
+JITCORE_PPC_REG_EXPAND(FPR17, 64)
+JITCORE_PPC_REG_EXPAND(FPR18, 64)
+JITCORE_PPC_REG_EXPAND(FPR19, 64)
+JITCORE_PPC_REG_EXPAND(FPR20, 64)
+JITCORE_PPC_REG_EXPAND(FPR21, 64)
+JITCORE_PPC_REG_EXPAND(FPR22, 64)
+JITCORE_PPC_REG_EXPAND(FPR23, 64)
+JITCORE_PPC_REG_EXPAND(FPR24, 64)
+JITCORE_PPC_REG_EXPAND(FPR25, 64)
+JITCORE_PPC_REG_EXPAND(FPR26, 64)
+JITCORE_PPC_REG_EXPAND(FPR27, 64)
+JITCORE_PPC_REG_EXPAND(FPR28, 64)
+JITCORE_PPC_REG_EXPAND(FPR29, 64)
+JITCORE_PPC_REG_EXPAND(FPR30, 64)
+JITCORE_PPC_REG_EXPAND(FPR31, 64)
+JITCORE_PPC_REG_EXPAND(FPSCR, 32)
+
+JITCORE_PPC_REG_EXPAND(VR0, 128)
+JITCORE_PPC_REG_EXPAND(VR1, 128)
+JITCORE_PPC_REG_EXPAND(VR2, 128)
+JITCORE_PPC_REG_EXPAND(VR3, 128)
+JITCORE_PPC_REG_EXPAND(VR4, 128)
+JITCORE_PPC_REG_EXPAND(VR5, 128)
+JITCORE_PPC_REG_EXPAND(VR6, 128)
+JITCORE_PPC_REG_EXPAND(VR7, 128)
+JITCORE_PPC_REG_EXPAND(VR8, 128)
+JITCORE_PPC_REG_EXPAND(VR9, 128)
+JITCORE_PPC_REG_EXPAND(VR10, 128)
+JITCORE_PPC_REG_EXPAND(VR11, 128)
+JITCORE_PPC_REG_EXPAND(VR12, 128)
+JITCORE_PPC_REG_EXPAND(VR13, 128)
+JITCORE_PPC_REG_EXPAND(VR14, 128)
+JITCORE_PPC_REG_EXPAND(VR15, 128)
+JITCORE_PPC_REG_EXPAND(VR16, 128)
+JITCORE_PPC_REG_EXPAND(VR17, 128)
+JITCORE_PPC_REG_EXPAND(VR18, 128)
+JITCORE_PPC_REG_EXPAND(VR19, 128)
+JITCORE_PPC_REG_EXPAND(VR20, 128)
+JITCORE_PPC_REG_EXPAND(VR21, 128)
+JITCORE_PPC_REG_EXPAND(VR22, 128)
+JITCORE_PPC_REG_EXPAND(VR23, 128)
+JITCORE_PPC_REG_EXPAND(VR24, 128)
+JITCORE_PPC_REG_EXPAND(VR25, 128)
+JITCORE_PPC_REG_EXPAND(VR26, 128)
+JITCORE_PPC_REG_EXPAND(VR27, 128)
+JITCORE_PPC_REG_EXPAND(VR28, 128)
+JITCORE_PPC_REG_EXPAND(VR29, 128)
+JITCORE_PPC_REG_EXPAND(VR30, 128)
+JITCORE_PPC_REG_EXPAND(VR31, 128)
+JITCORE_PPC_REG_EXPAND(VRSAVE, 32)
+JITCORE_PPC_REG_EXPAND(VSCR, 32)