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authorFabrice Desclaux <fabrice.desclaux@cea.fr>2016-10-21 16:19:09 +0200
committerFabrice Desclaux <fabrice.desclaux@cea.fr>2016-11-04 16:45:46 +0100
commit3771288cffdd53c1ff87857374bd13c550b355dc (patch)
treeb85469ca5e38aeb54e19d24ccb4bea1ecf627b5e /test/arch/arm/sem.py
parent589d4fd9ebd61216155bba9f1988bbd5c3094a2b (diff)
downloadmiasm-3771288cffdd53c1ff87857374bd13c550b355dc.tar.gz
miasm-3771288cffdd53c1ff87857374bd13c550b355dc.zip
ExprCompose: add new api
The ExprComposes uses directly its arguments sizes to guess the slices
locations.
Old api:  ExprCompose([(a, 0, 32), (b, 32, 64)])
becomes:  ExprCompose(a, b)
Diffstat (limited to 'test/arch/arm/sem.py')
-rw-r--r--test/arch/arm/sem.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py
index cefbe76a..8fc609fb 100644
--- a/test/arch/arm/sem.py
+++ b/test/arch/arm/sem.py
@@ -285,7 +285,7 @@ class TestARMSemantic(unittest.TestCase):
         self.assertEqual(compute('AND                R4,    R4,   R5    LSR 2 ',  {R4: 0xFFFFFFFF, R5: 0x80000041, }), {R4: 0x20000010, R5: 0x80000041, })
         self.assertEqual(compute('AND                R4,    R4,   R5    ASR 3 ',  {R4: 0xF00000FF, R5: 0x80000081, }), {R4: 0xF0000010, R5: 0x80000081, })
         self.assertEqual(compute('AND                R4,    R4,   R5    ROR 4 ',  {R4: 0xFFFFFFFF, R5: 0x000000FF, }), {R4: 0xF000000F, R5: 0x000000FF, })
-        self.assertEqual(compute('AND                R4,    R4,   R5    RRX   ',  {R4: 0xFFFFFFFF, R5: 0x00000101, }), {R4: ExprCompose([(ExprInt(0x80, 31),0,31), (cf_init,31,32)]), R5: 0x00000101, })
+        self.assertEqual(compute('AND                R4,    R4,   R5    RRX   ',  {R4: 0xFFFFFFFF, R5: 0x00000101, }), {R4: ExprCompose(ExprInt(0x80, 31), cf_init), R5: 0x00000101, })
 
         # §A8.8.15:                AND{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <type> <Rs>
         self.assertEqual(compute('AND                R4,    R6,   R4    LSL R5',  {R4: 0x00000001, R5: 0x00000004, R6: -1, }), {R4: 0x00000010, R5: 0x00000004, R6: 0xFFFFFFFF, })