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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2015-10-29 10:35:32 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2015-10-29 13:37:03 +0100 |
| commit | c4e4273c2d4e459eddc96c8ef0af0e5eff9c3f7e (patch) | |
| tree | eae7ae526c7e45d1e640c814ec3a03d5b999fac8 /test/arch/arm/sem.py | |
| parent | e37d545e07a22b0ea9a5ce21b975c73927dd4d50 (diff) | |
| download | miasm-c4e4273c2d4e459eddc96c8ef0af0e5eff9c3f7e.tar.gz miasm-c4e4273c2d4e459eddc96c8ef0af0e5eff9c3f7e.zip | |
Expression: fix api
Diffstat (limited to 'test/arch/arm/sem.py')
| -rw-r--r-- | test/arch/arm/sem.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py index 51c42fd1..feef7372 100644 --- a/test/arch/arm/sem.py +++ b/test/arch/arm/sem.py @@ -16,7 +16,7 @@ EXCLUDE_REGS = set([ir_arch().IRDst]) def M(addr): - return ExprMem(ExprInt_fromsize(16, addr), 16) + return ExprMem(ExprInt(addr, 16), 16) def compute(asm, inputstate={}, debug=False): @@ -285,7 +285,7 @@ class TestARMSemantic(unittest.TestCase): self.assertEqual(compute('AND R4, R4, R5 LSR 2 ', {R4: 0xFFFFFFFF, R5: 0x80000041, }), {R4: 0x20000010, R5: 0x80000041, }) self.assertEqual(compute('AND R4, R4, R5 ASR 3 ', {R4: 0xF00000FF, R5: 0x80000081, }), {R4: 0xF0000010, R5: 0x80000081, }) self.assertEqual(compute('AND R4, R4, R5 ROR 4 ', {R4: 0xFFFFFFFF, R5: 0x000000FF, }), {R4: 0xF000000F, R5: 0x000000FF, }) - self.assertEqual(compute('AND R4, R4, R5 RRX ', {R4: 0xFFFFFFFF, R5: 0x00000101, }), {R4: ExprCompose([(ExprInt_fromsize(31, 0x80),0,31), (cf_init,31,32)]), R5: 0x00000101, }) + self.assertEqual(compute('AND R4, R4, R5 RRX ', {R4: 0xFFFFFFFF, R5: 0x00000101, }), {R4: ExprCompose([(ExprInt(0x80, 31),0,31), (cf_init,31,32)]), R5: 0x00000101, }) # §A8.8.15: AND{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <type> <Rs> self.assertEqual(compute('AND R4, R6, R4 LSL R5', {R4: 0x00000001, R5: 0x00000004, R6: -1, }), {R4: 0x00000010, R5: 0x00000004, R6: 0xFFFFFFFF, }) |