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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
| commit | 6e09df71a333bf87cd68c2d08ad068a3e501462d (patch) | |
| tree | 7d76e0626e61ef5a9f15c62358337674fb0095aa /test/arch/x86/sem.py | |
| parent | e8d0fcf8d28d82a8f33138d044f335634ac3a30c (diff) | |
| download | miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.tar.gz miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.zip | |
Modify irbloc destination mecanism. Rework API in consequence.
Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
Diffstat (limited to 'test/arch/x86/sem.py')
| -rw-r--r-- | test/arch/x86/sem.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py index 64447e13..bd28bd45 100644 --- a/test/arch/x86/sem.py +++ b/test/arch/x86/sem.py @@ -17,7 +17,7 @@ from miasm2.core import parse_asm, asmbloc logging.getLogger('cpuhelper').setLevel(logging.ERROR) -EXCLUDE_REGS = set() +EXCLUDE_REGS = set([ir_32().IRDst, ir_64().IRDst]) m32 = 32 m64 = 64 @@ -25,7 +25,7 @@ m64 = 64 def symb_exec(interm, inputstate, debug): sympool = dict(regs_init) sympool.update(inputstate) - symexec = symbexec(mn, sympool) + symexec = symbexec(interm, sympool) symexec.emul_ir_blocs(interm, 0) if debug: for k, v in symexec.symbols.items(): |