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| author | Ajax <commial@gmail.com> | 2017-06-27 12:28:01 +0200 |
|---|---|---|
| committer | Ajax <commial@gmail.com> | 2017-06-27 12:42:57 +0200 |
| commit | 04fc16be01be380b4b25d795f271c38e8dabc79f (patch) | |
| tree | 17d4f1e9112257ca1a3ee38e9471bf100f8061fc /test/arch/x86/unit/mn_div.py | |
| parent | 5520569d1c6d969fecd968557fd2251e9d1399ee (diff) | |
| download | miasm-04fc16be01be380b4b25d795f271c38e8dabc79f.tar.gz miasm-04fc16be01be380b4b25d795f271c38e8dabc79f.zip | |
Add a regression test for DIV 128bits
Diffstat (limited to 'test/arch/x86/unit/mn_div.py')
| -rw-r--r-- | test/arch/x86/unit/mn_div.py | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/arch/x86/unit/mn_div.py b/test/arch/x86/unit/mn_div.py new file mode 100644 index 00000000..84569607 --- /dev/null +++ b/test/arch/x86/unit/mn_div.py @@ -0,0 +1,17 @@ +import sys +from asm_test import Asm_Test_64 + +class Test_DIV(Asm_Test_64): + TXT = ''' +main: + MOV RAX, 0x8877665544332211 + MOV RBX, 0x11223344556677 + DIV RBX + RET + ''' + def check(self): + assert self.myjit.cpu.RAX == 0x7F7 + assert self.myjit.cpu.RDX == 0x440 + +if __name__ == "__main__": + [test(*sys.argv[1:])() for test in [Test_DIV]] |