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| author | Camille Mougey <commial@gmail.com> | 2018-06-09 09:05:05 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-06-09 09:05:05 +0200 |
| commit | 990060f21e515ff1a25246f8fdf0936a97ac698f (patch) | |
| tree | b10543391f9a66ddd5e3f6852c30d96b169b623d /test/arch/x86/unit/mn_pushpop.py | |
| parent | dadfaabc3fff5edb9bf4ef7e7e8c4cfc4baccb94 (diff) | |
| parent | 61551fa78e9dd22ed1f982b4fe171fd6383c39a6 (diff) | |
| download | miasm-990060f21e515ff1a25246f8fdf0936a97ac698f.tar.gz miasm-990060f21e515ff1a25246f8fdf0936a97ac698f.zip | |
Merge pull request #751 from serpilliere/ExprLabel
Expr Loc
Diffstat (limited to 'test/arch/x86/unit/mn_pushpop.py')
| -rwxr-xr-x | test/arch/x86/unit/mn_pushpop.py | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/arch/x86/unit/mn_pushpop.py b/test/arch/x86/unit/mn_pushpop.py index 7ac400c0..bed70ea3 100755 --- a/test/arch/x86/unit/mn_pushpop.py +++ b/test/arch/x86/unit/mn_pushpop.py @@ -21,7 +21,7 @@ class Test_PUSHAD_32(Asm_Test_32): MYSTRING = "test pushad 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -48,7 +48,7 @@ class Test_PUSHA_32(Asm_Test_32): MYSTRING = "test pusha 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -75,7 +75,7 @@ class Test_PUSHA_16(Asm_Test_16): MYSTRING = "test pusha 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -102,7 +102,7 @@ class Test_PUSHAD_16(Asm_Test_16): MYSTRING = "test pushad 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -129,7 +129,7 @@ class Test_PUSH_mode32_32(Asm_Test_32): MYSTRING = "test push mode32 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -152,7 +152,7 @@ class Test_PUSH_mode32_16(Asm_Test_32): MYSTRING = "test push mode32 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -175,7 +175,7 @@ class Test_PUSH_mode16_16(Asm_Test_16): MYSTRING = "test push mode16 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -198,7 +198,7 @@ class Test_PUSH_mode16_32(Asm_Test_16): MYSTRING = "test push mode16 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): init_regs(self) @@ -221,7 +221,7 @@ class Test_POP_mode32_32(Asm_Test_32): MYSTRING = "test pop mode32 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x11223344 @@ -243,7 +243,7 @@ class Test_POP_mode32_16(Asm_Test_32): MYSTRING = "test pop mode32 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x1122 @@ -265,7 +265,7 @@ class Test_POP_mode16_16(Asm_Test_16): MYSTRING = "test pop mode16 16" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x1122 @@ -287,7 +287,7 @@ class Test_POP_mode16_32(Asm_Test_16): MYSTRING = "test pop mode16 32" def prepare(self): - self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr) + self.myjit.ir_arch.symbol_pool.add_location("lbl_ret", self.ret_addr) def test_init(self): self.value = 0x11223344 |