Merge pull request #558 from serpilliere/fix_x86_segm

Fix x86 segm

1 files changed, 194 insertions, 1 deletions

diff --git a/test/arch/x86/unit/mn_pushpop.py b/test/arch/x86/unit/mn_pushpop.py
index ffcc3fa5..7ac400c0 100755
--- a/test/arch/x86/unit/mn_pushpop.py
+++ b/test/arch/x86/unit/mn_pushpop.py
@@ -39,6 +39,7 @@ class Test_PUSHAD_32(Asm_Test_32):
     '''
 
     def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin - 0x4 * 8
         buf = self.myjit.vm.get_mem(self.myjit.cpu.ESP, 0x4 * 8)
         assert(buf == self.buf)
 
@@ -65,6 +66,7 @@ class Test_PUSHA_32(Asm_Test_32):
     '''
 
     def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin - 0x2 * 8
         buf = self.myjit.vm.get_mem(self.myjit.cpu.ESP, 0x2 * 8)
         assert(buf == self.buf)
 
@@ -91,6 +93,7 @@ class Test_PUSHA_16(Asm_Test_16):
     '''
 
     def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin - 0x2 * 8
         buf = self.myjit.vm.get_mem(self.myjit.cpu.SP, 0x2 * 8)
         assert(buf == self.buf)
 
@@ -117,12 +120,202 @@ class Test_PUSHAD_16(Asm_Test_16):
     '''
 
     def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin - 0x4 * 8
         buf = self.myjit.vm.get_mem(self.myjit.cpu.SP, 0x4 * 8)
         assert(buf == self.buf)
 
 
+class Test_PUSH_mode32_32(Asm_Test_32):
+    MYSTRING = "test push mode32 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        init_regs(self)
+        self.buf = ""
+        self.buf += pck32(0x11223344)
+
+    TXT = '''
+    main:
+       PUSH 0x11223344
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin - 0x4
+        buf = self.myjit.vm.get_mem(self.myjit.cpu.ESP, 0x4)
+        assert(buf == self.buf)
+
+
+class Test_PUSH_mode32_16(Asm_Test_32):
+    MYSTRING = "test push mode32 16"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        init_regs(self)
+        self.buf = ""
+        self.buf += pck16(0x1122)
+
+    TXT = '''
+    main:
+       PUSHW 0x1122
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin - 0x2
+        buf = self.myjit.vm.get_mem(self.myjit.cpu.ESP, 0x2)
+        assert(buf == self.buf)
+
+
+class Test_PUSH_mode16_16(Asm_Test_16):
+    MYSTRING = "test push mode16 16"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        init_regs(self)
+        self.buf = ""
+        self.buf += pck16(0x1122)
+
+    TXT = '''
+    main:
+       PUSHW 0x1122
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin - 0x2
+        buf = self.myjit.vm.get_mem(self.myjit.cpu.ESP, 0x2)
+        assert(buf == self.buf)
+
+
+class Test_PUSH_mode16_32(Asm_Test_16):
+    MYSTRING = "test push mode16 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        init_regs(self)
+        self.buf = ""
+        self.buf += pck32(0x11223344)
+
+    TXT = '''
+    main:
+       .byte 0x66, 0x68, 0x44, 0x33, 0x22, 0x11
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin - 0x4
+        buf = self.myjit.vm.get_mem(self.myjit.cpu.ESP, 0x4)
+        assert(buf == self.buf)
+
+
+class Test_POP_mode32_32(Asm_Test_32):
+    MYSTRING = "test pop mode32 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.value = 0x11223344
+        self.myjit.push_uint32_t(self.value)
+        init_regs(self)
+
+    TXT = '''
+    main:
+       POP EAX
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin + 0x4
+        assert self.myjit.cpu.EAX == self.value
+
+
+class Test_POP_mode32_16(Asm_Test_32):
+    MYSTRING = "test pop mode32 16"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.value = 0x1122
+        self.myjit.push_uint16_t(self.value)
+        init_regs(self)
+
+    TXT = '''
+    main:
+       POPW AX
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin + 0x2
+        assert self.myjit.cpu.AX == self.value
+
+
+class Test_POP_mode16_16(Asm_Test_16):
+    MYSTRING = "test pop mode16 16"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.value = 0x1122
+        self.myjit.push_uint16_t(self.value)
+        init_regs(self)
+
+    TXT = '''
+    main:
+       POPW AX
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin + 0x2
+        assert self.myjit.cpu.AX == self.value
+
+
+class Test_POP_mode16_32(Asm_Test_16):
+    MYSTRING = "test pop mode16 32"
+
+    def prepare(self):
+        self.myjit.ir_arch.symbol_pool.add_label("lbl_ret", self.ret_addr)
+
+    def test_init(self):
+        self.value = 0x11223344
+        self.myjit.cpu.SP -= 0x4
+        self.myjit.vm.set_mem(self.myjit.cpu.SP, pck32(self.value))
+        init_regs(self)
+
+    TXT = '''
+    main:
+       POP EAX
+       JMP lbl_ret
+    '''
+
+    def check(self):
+        assert self.myjit.cpu.ESP == self.stk_origin + 0x4
+        assert self.myjit.cpu.EAX == self.value
+
+
 if __name__ == "__main__":
     [test(*sys.argv[1:])() for test in [Test_PUSHA_16, Test_PUSHA_32,
-                                        Test_PUSHAD_16, Test_PUSHAD_32
+                                        Test_PUSHAD_16, Test_PUSHAD_32,
+                                        Test_PUSH_mode32_32,
+                                        Test_PUSH_mode32_16,
+                                        Test_PUSH_mode16_16,
+                                        Test_PUSH_mode16_32,
+                                        Test_POP_mode32_32,
+                                        Test_POP_mode32_16,
+                                        Test_POP_mode16_16,
+                                        Test_POP_mode16_32,
                                         ]
     ]