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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2015-12-23 19:48:04 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2015-12-24 18:38:19 +0100 |
| commit | 51a38b43d5ab72831828c1bd4dad169968f8197d (patch) | |
| tree | 2d1d74ff96b6d6936df7bbdab236629095f005a9 /test | |
| parent | 389c1230cf87fc8535ac1bdc1c2ffad08dd70ae2 (diff) | |
| download | miasm-51a38b43d5ab72831828c1bd4dad169968f8197d.tar.gz miasm-51a38b43d5ab72831828c1bd4dad169968f8197d.zip | |
X86: add psrl/psll
Diffstat (limited to 'test')
| -rw-r--r-- | test/arch/x86/arch.py | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index a38cbcf3..3dd91581 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -2592,6 +2592,67 @@ reg_tests = [ "660F380036"), + (m32, "00000000 PSRLQ MM6, 0x5", + "0F73D605"), + (m32, "00000000 PSRLQ XMM6, 0x5", + "660F73D605"), + (m32, "00000000 PSRLD MM6, 0x5", + "0F72D605"), + (m32, "00000000 PSRLD XMM6, 0x5", + "660F72D605"), + (m32, "00000000 PSRLW MM6, 0x5", + "0F71D605"), + (m32, "00000000 PSRLW XMM6, 0x5", + "660F71D605"), + + + (m32, "00000000 PSRLQ MM2, QWORD PTR [EDX]", + "0FD312"), + (m32, "00000000 PSRLQ XMM2, XMMWORD PTR [EDX]", + "660FD312"), + + (m32, "00000000 PSRLD MM2, QWORD PTR [EDX]", + "0FD212"), + (m32, "00000000 PSRLD XMM2, XMMWORD PTR [EDX]", + "660FD212"), + + (m32, "00000000 PSRLW MM2, QWORD PTR [EDX]", + "0FD112"), + (m32, "00000000 PSRLW XMM2, XMMWORD PTR [EDX]", + "660FD112"), + + + + + (m32, "00000000 PSLLQ MM6, 0x5", + "0F73F605"), + (m32, "00000000 PSLLQ XMM6, 0x5", + "660F73F605"), + (m32, "00000000 PSLLD MM6, 0x5", + "0F72F605"), + (m32, "00000000 PSLLD XMM6, 0x5", + "660F72F605"), + (m32, "00000000 PSLLW MM6, 0x5", + "0F71F605"), + (m32, "00000000 PSLLW XMM6, 0x5", + "660F71F605"), + + + (m32, "00000000 PSLLQ MM2, QWORD PTR [EDX]", + "0FF312"), + (m32, "00000000 PSLLQ XMM2, XMMWORD PTR [EDX]", + "660FF312"), + + (m32, "00000000 PSLLD MM2, QWORD PTR [EDX]", + "0FF212"), + (m32, "00000000 PSLLD XMM2, XMMWORD PTR [EDX]", + "660FF212"), + + (m32, "00000000 PSLLW MM2, QWORD PTR [EDX]", + "0FF112"), + (m32, "00000000 PSLLW XMM2, XMMWORD PTR [EDX]", + "660FF112"), + ] |