diff options
Diffstat (limited to '')
| -rw-r--r-- | miasm/arch/arm/regs.py | 32 | ||||
| -rw-r--r-- | miasm/arch/arm/sem.py | 100 |
2 files changed, 131 insertions, 1 deletions
diff --git a/miasm/arch/arm/regs.py b/miasm/arch/arm/regs.py index 63caada3..60c911bc 100644 --- a/miasm/arch/arm/regs.py +++ b/miasm/arch/arm/regs.py @@ -2,7 +2,7 @@ from builtins import range from miasm.expression.expression import * - +from miasm.core.cpu import gen_reg, gen_regs # GP @@ -111,4 +111,34 @@ regs_init = {} for i, r in enumerate(all_regs_ids): regs_init[r] = all_regs_ids_init[i] +coproc_reg_str = [ + "MIDR", "CTR", "TCMTR", "TLBTR", "MPIDR", "REVIDR", + "ID_PFR0", "ID_PFR1", "ID_AFR0", "ID_DFR0", "ID_MMFR0", "ID_MMFR1", "ID_MMFR2", "ID_MMFR3", + "ID_ISAR0", "ID_ISAR1", "ID_ISAR2", "ID_ISAR3", "ID_ISAR4", "ID_ISAR5", + "CCSIDR", "CLIDR", "AIDR", + "CSSELR", + "SCTLR", + "TTBR0", "TTBR1", "TTBCR", + "HTCR", "VTCR", + "DACR", + "DFSR", "IFSR", "ADFSR", "AIFSR", + "HADFSR", "HAIFSR", "HSR", + "DFAR", "IFAR", + "HDFAR", "HIFAR", "HPFAR", + "AMAIR0", "AMAIR1", + "PRRR", "NMRR", # Alias MAIR0/MAIR1 + "HMAIR0", "HMAIR1", "HAMAIR0", "HAMAIR1", + "VBAR", "MVBAR", "ISR", + "HVBAR", + "CONTEXTIDR" + ] +coproc_reg_expr, coproc_reg_init, coproc_reg_info = gen_regs(coproc_reg_str, globals(), 32) + +all_regs_ids = all_regs_ids + coproc_reg_expr +all_regs_ids_byname.update(dict([(x.name, x) for x in coproc_reg_expr])) +all_regs_ids_init = all_regs_ids_init + coproc_reg_init + +for i, r in enumerate(coproc_reg_expr): + regs_init[r] = coproc_reg_init[i] + regs_flt_expr = [] diff --git a/miasm/arch/arm/sem.py b/miasm/arch/arm/sem.py index 569a9a23..ae687c6d 100644 --- a/miasm/arch/arm/sem.py +++ b/miasm/arch/arm/sem.py @@ -8,6 +8,84 @@ from miasm.arch.arm.regs import * from miasm.jitter.csts import EXCEPT_DIV_BY_ZERO, EXCEPT_INT_XX +coproc_reg_dict = { + ("p15", 0, "c0", "c0", 0): MIDR, + ("p15", 0, "c0", "c0", 1): CTR, + ("p15", 0, "c0", "c0", 2): TCMTR, + ("p15", 0, "c0", "c0", 3): TLBTR, + ("p15", 0, "c0", "c0", 4): MIDR, + ("p15", 0, "c0", "c0", 5): MPIDR, + ("p15", 0, "c0", "c0", 6): REVIDR, + + ("p15", 0, "c0", "c1", 0): ID_PFR0, + ("p15", 0, "c0", "c1", 1): ID_PFR1, + ("p15", 0, "c0", "c1", 2): ID_DFR0, + ("p15", 0, "c0", "c1", 3): ID_AFR0, + ("p15", 0, "c0", "c1", 4): ID_MMFR0, + ("p15", 0, "c0", "c1", 5): ID_MMFR1, + ("p15", 0, "c0", "c1", 6): ID_MMFR2, + ("p15", 0, "c0", "c1", 7): ID_MMFR3, + + ("p15", 0, "c0", "c2", 0): ID_ISAR0, + ("p15", 0, "c0", "c2", 1): ID_ISAR1, + ("p15", 0, "c0", "c2", 2): ID_ISAR2, + ("p15", 0, "c0", "c2", 3): ID_ISAR3, + ("p15", 0, "c0", "c2", 4): ID_ISAR4, + ("p15", 0, "c0", "c2", 5): ID_ISAR5, + + ("p15", 1, "c0", "c0", 0): CCSIDR, + ("p15", 1, "c0", "c0", 1): CLIDR, + ("p15", 1, "c0", "c0", 7): AIDR, + + ("p15", 2, "c0", "c0", 0): CSSELR, + + ("p15", 0, "c1", "c0", 0): SCTLR, + + ("p15", 0, "c2", "c0", 0): TTBR0, + ("p15", 0, "c2", "c0", 1): TTBR1, + ("p15", 0, "c2", "c0", 2): TTBCR, + + ("p15", 4, "c2", "c0", 2): HTCR, + ("p15", 4, "c2", "c1", 2): VTCR, + + ("p15", 0, "c3", "c0", 0): DACR, + + ("p15", 0, "c5", "c0", 0): DFSR, + ("p15", 0, "c5", "c0", 1): IFSR, + ("p15", 0, "c5", "c1", 0): ADFSR, + ("p15", 0, "c5", "c1", 1): AIFSR, + + ("p15", 4, "c5", "c1", 0): HADFSR, + ("p15", 4, "c5", "c1", 1): HAIFSR, + ("p15", 4, "c5", "c2", 0): HSR, + + ("p15", 0, "c6", "c0", 0): DFAR, + ("p15", 0, "c6", "c0", 2): IFAR, + + ("p15", 4, "c6", "c0", 0): HDFAR, + ("p15", 4, "c6", "c0", 2): HIFAR, + ("p15", 4, "c6", "c0", 4): HPFAR, + + ("p15", 0, "c10", "c3", 0): AMAIR0, + ("p15", 0, "c10", "c3", 1): AMAIR1, + + ("p15", 0, "c10", "c2", 0): PRRR, # ALIAS MAIR0 + ("p15", 0, "c10", "c2", 1): NMRR, # ALIAS MAIR1 + + ("p15", 4, "c10", "c2", 0): HMAIR0, + ("p15", 4, "c10", "c2", 1): HMAIR1, + ("p15", 4, "c10", "c3", 0): HAMAIR0, + ("p15", 4, "c10", "c3", 1): HAMAIR1, + + ("p15", 0, "c12", "c0", 0): VBAR, + ("p15", 0, "c12", "c0", 1): MVBAR, + ("p15", 0, "c12", "c1", 0): ISR, + + ("p15", 4, "c12", "c0", 0): HVBAR, + + ("p15", 0, "c13", "c0", 1): CONTEXTIDR + } + # liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf EXCEPT_SOFT_BP = (1 << 1) @@ -1376,6 +1454,25 @@ def pkhtb(ir, instr, arg1, arg2, arg3): ) return e, [] +def mcr(ir, insr, arg1, arg2, arg3, arg4, arg5, arg6): + e = [] + sreg = (str(arg1), int(arg2), str(arg4), str(arg5), int(arg6)) + if sreg in coproc_reg_dict: + e.append(ExprAssign(arg3, coproc_reg_dict[sreg])) + else: + raise NotImplementedError("Unknown coprocessor register") + + return e, [] + +def mrc(ir, insr, arg1, arg2, arg3, arg4, arg5, arg6): + e = [] + sreg = (str(arg1), int(arg2), str(arg4), str(arg5), int(arg6)) + if sreg in coproc_reg_dict: + e.append(ExprAssign(coproc_reg_dict[sreg], arg3)) + else: + raise NotImplementedError("Unknown coprocessor register") + + return e, [] COND_EQ = 0 COND_NE = 1 @@ -1574,6 +1671,9 @@ mnemo_condm1 = {'adds': add, 'bics': bics, 'mvns': mvns, + 'mrc': mrc, + 'mcr': mcr, + 'mrs': mrs, 'msr': msr, |