diff options
| -rw-r--r-- | miasm2/arch/x86/jit.py | 2 | ||||
| -rw-r--r-- | miasm2/ir/ir.py | 3 | ||||
| -rw-r--r-- | miasm2/jitter/JitCore.h | 13 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_x86.c | 4 | ||||
| -rw-r--r-- | test/ir/ir.py | 1 |
5 files changed, 14 insertions, 9 deletions
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index 1329d7a4..6d9be8ac 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -127,7 +127,7 @@ class jitter_x86_32(jitter): return ret_ad, args def func_ret_cdecl(self, ret_addr, ret_value=None): - self.cpu.EIP = ret_addr + self.pc = self.cpu.EIP = ret_addr if ret_value is not None: self.cpu.EAX = ret_value diff --git a/miasm2/ir/ir.py b/miasm2/ir/ir.py index bc23d471..e5f0c8db 100644 --- a/miasm2/ir/ir.py +++ b/miasm2/ir/ir.py @@ -139,6 +139,9 @@ class AssignBlock(object): for dst, src in self._assigns.iteritems(): yield dst, src + def items(self): + return [(dst, src) for dst, src in self.iteritems()] + def itervalues(self): for src in self._assigns.itervalues(): yield src diff --git a/miasm2/jitter/JitCore.h b/miasm2/jitter/JitCore.h index 24feb9c0..f599d6ea 100644 --- a/miasm2/jitter/JitCore.h +++ b/miasm2/jitter/JitCore.h @@ -17,7 +17,7 @@ } \ -#define PyGetInt_ret0(item, value) \ +#define PyGetInt_retneg(item, value) \ if (PyInt_Check(item)){ \ value = (uint64_t)PyInt_AsLong(item); \ } \ @@ -25,7 +25,8 @@ value = (uint64_t)PyLong_AsUnsignedLongLong(item); \ } \ else{ \ - printf("error\n"); return 0; \ + PyErr_SetString(PyExc_TypeError, "Arg must be int"); \ + return -1; \ } \ @@ -38,7 +39,7 @@ static int JitCpu_set_ ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint64_t val; \ - PyGetInt_ret0(value, val); \ + PyGetInt_retneg(value, val); \ ((vm_cpu_t*)(self->cpu))-> regname = val; \ return 0; \ } @@ -51,7 +52,7 @@ static int JitCpu_set_ ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint32_t val; \ - PyGetInt_ret0(value, val); \ + PyGetInt_retneg(value, val); \ ((vm_cpu_t*)(self->cpu))-> regname = val; \ return 0; \ } @@ -65,8 +66,8 @@ static int JitCpu_set_ ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint16_t val; \ - PyGetInt_ret0(value, val); \ - ((vm_cpu_t*)(self->cpu))-> regname = val; \ + PyGetInt_retneg(value, val); \ + ((vm_cpu_t*)(self->cpu))-> regname = val; \ return 0; \ } diff --git a/miasm2/jitter/arch/JitCore_x86.c b/miasm2/jitter/arch/JitCore_x86.c index 95cb18bd..3198eff3 100644 --- a/miasm2/jitter/arch/JitCore_x86.c +++ b/miasm2/jitter/arch/JitCore_x86.c @@ -428,7 +428,7 @@ JitCpu_init(JitCpu *self, PyObject *args, PyObject *kwds) static int JitCpu_set_E ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint64_t val; \ - PyGetInt_ret0(value, val); \ + PyGetInt_retneg(value, val); \ val &= 0xFFFFFFFF; \ val |= ((vm_cpu_t*)(self->cpu))->R ##regname & 0xFFFFFFFF00000000ULL; \ ((vm_cpu_t*)(self->cpu))->R ## regname = val; \ @@ -445,7 +445,7 @@ JitCpu_init(JitCpu *self, PyObject *args, PyObject *kwds) static int JitCpu_set_ ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint64_t val; \ - PyGetInt_ret0(value, val); \ + PyGetInt_retneg(value, val); \ val &= 0xFFFF; \ val |= ((vm_cpu_t*)(self->cpu))->R ##regname & 0xFFFFFFFFFFFF0000ULL; \ ((vm_cpu_t*)(self->cpu))->R ## regname = val; \ diff --git a/test/ir/ir.py b/test/ir/ir.py index 5c428a94..05936d75 100644 --- a/test/ir/ir.py +++ b/test/ir/ir.py @@ -37,6 +37,7 @@ assert assignblk1.get_rw() == {id_a: set([id_b])} assert assignblk1.keys() == [id_a] assert dict(assignblk1) == {id_a: id_b} assert assignblk1[id_a] == id_b +assert list(assignblk1.iteritems()) == assignblk1.items() ## Simplify assignblk3 = AssignBlock({id_a: id_b - id_b}) |