diff options
36 files changed, 117 insertions, 143 deletions
diff --git a/README.md b/README.md index c31bdc26..dd956254 100644 --- a/README.md +++ b/README.md @@ -125,7 +125,7 @@ Add instruction to the pool: Print current pool: ```pycon >>> for lbl, irblock in ircfg.blocks.items(): -... print(irblock.to_string(loc_db)) +... print(irblock) loc_0: R2 = R8 + R0 @@ -134,10 +134,10 @@ IRDst = loc_4 ``` Working with IR, for instance by getting side effects: ```pycon ->>> for lbl, irblock in ircfg.blocks.iteritems(): +>>> for lbl, irblock in ircfg.blocks.items(): ... for assignblk in irblock: ... rw = assignblk.get_rw() -... for dst, reads in rw.iteritems(): +... for dst, reads in rw.items(): ... print('read: ', [str(x) for x in reads]) ... print('written:', dst) ... print() @@ -166,7 +166,7 @@ Giving a shellcode: 00000010 8d5b01 lea ebx, [ebx+0x1] 00000013 89d8 mov eax, ebx 00000015 c3 ret ->>> s = '\x8dI\x04\x8d[\x01\x80\xf9\x01t\x05\x8d[\xff\xeb\x03\x8d[\x01\x89\xd8\xc3' +>>> s = b'\x8dI\x04\x8d[\x01\x80\xf9\x01t\x05\x8d[\xff\xeb\x03\x8d[\x01\x89\xd8\xc3' ``` Import the shellcode thanks to the `Container` abstraction: @@ -185,7 +185,7 @@ Disassembling the shellcode at address `0`: >>> mdis = machine.dis_engine(c.bin_stream, loc_db=loc_db) >>> asmcfg = mdis.dis_multiblock(0) >>> for block in asmcfg.blocks: -... print(block.to_string(asmcfg.loc_db)) +... print(block) ... loc_0 LEA ECX, DWORD PTR [ECX + 0x4] diff --git a/example/asm/shellcode.py b/example/asm/shellcode.py index d33d6231..70d844a9 100755 --- a/example/asm/shellcode.py +++ b/example/asm/shellcode.py @@ -106,7 +106,6 @@ open("graph.dot", "w").write(asmcfg.dot()) patches = asmblock.asm_resolve_final( machine.mn, asmcfg, - loc_db, dst_interval ) if args.encrypt: diff --git a/example/asm/simple.py b/example/asm/simple.py index 6197556b..bfa3ace6 100644 --- a/example/asm/simple.py +++ b/example/asm/simple.py @@ -30,7 +30,7 @@ loop: loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) # Spread information and resolve instructions offset -patches = asmblock.asm_resolve_final(mn_x86, asmcfg, loc_db) +patches = asmblock.asm_resolve_final(mn_x86, asmcfg) # Show resolved asmcfg for block in asmcfg.blocks: diff --git a/example/expression/asm_to_ir.py b/example/expression/asm_to_ir.py index edc23437..8ecc4f24 100644 --- a/example/expression/asm_to_ir.py +++ b/example/expression/asm_to_ir.py @@ -40,7 +40,7 @@ for block in asmcfg.blocks: print("symbols:") print(loc_db) -patches = asmblock.asm_resolve_final(mn_x86, asmcfg, loc_db) +patches = asmblock.asm_resolve_final(mn_x86, asmcfg) # Translate to IR ir_arch = ir_a_x86_32(loc_db) diff --git a/miasm/analysis/data_flow.py b/miasm/analysis/data_flow.py index 49384a8b..40153f8b 100644 --- a/miasm/analysis/data_flow.py +++ b/miasm/analysis/data_flow.py @@ -1062,10 +1062,10 @@ class DiGraphLiveness(DiGraph): DiGraph representing variable liveness """ - def __init__(self, ircfg, loc_db=None): + def __init__(self, ircfg): super(DiGraphLiveness, self).__init__() self.ircfg = ircfg - self.loc_db = loc_db + self.loc_db = ircfg.loc_db self._blocks = {} # Add irblocks gen/kill for node in ircfg.nodes(): @@ -1092,14 +1092,11 @@ class DiGraphLiveness(DiGraph): """ Output liveness information in dot format """ - if self.loc_db is None: - node_name = str(node) + names = self.loc_db.get_location_names(node) + if not names: + node_name = self.loc_db.pretty_str(node) else: - names = self.loc_db.get_location_names(node) - if not names: - node_name = self.loc_db.pretty_str(node) - else: - node_name = "".join("%s:\n" % name for name in names) + node_name = "".join("%s:\n" % name for name in names) yield self.DotCellDescription( text="%s" % node_name, attr={ diff --git a/miasm/arch/aarch64/ira.py b/miasm/arch/aarch64/ira.py index e20a0943..aded3dd1 100644 --- a/miasm/arch/aarch64/ira.py +++ b/miasm/arch/aarch64/ira.py @@ -6,21 +6,21 @@ from miasm.arch.aarch64.sem import ir_aarch64l, ir_aarch64b class ir_a_aarch64l_base(ir_aarch64l, ira): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_aarch64l.__init__(self, loc_db) self.ret_reg = self.arch.regs.X0 class ir_a_aarch64b_base(ir_aarch64b, ira): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_aarch64b.__init__(self, loc_db) self.ret_reg = self.arch.regs.X0 class ir_a_aarch64l(ir_a_aarch64l_base): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_a_aarch64l_base.__init__(self, loc_db) self.ret_reg = self.arch.regs.X0 @@ -45,6 +45,6 @@ class ir_a_aarch64l(ir_a_aarch64l_base): class ir_a_aarch64b(ir_a_aarch64b_base, ir_a_aarch64l): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_a_aarch64b_base.__init__(self, loc_db) self.ret_reg = self.arch.regs.X0 diff --git a/miasm/arch/aarch64/sem.py b/miasm/arch/aarch64/sem.py index e77df911..8ce72638 100644 --- a/miasm/arch/aarch64/sem.py +++ b/miasm/arch/aarch64/sem.py @@ -2228,7 +2228,7 @@ class aarch64info(object): class ir_aarch64l(IntermediateRepresentation): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_aarch64, "l", loc_db) self.pc = PC self.sp = SP @@ -2314,7 +2314,7 @@ class ir_aarch64l(IntermediateRepresentation): class ir_aarch64b(ir_aarch64l): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_aarch64, "b", loc_db) self.pc = PC self.sp = SP diff --git a/miasm/arch/arm/ira.py b/miasm/arch/arm/ira.py index 178e8abc..f2d8d44b 100644 --- a/miasm/arch/arm/ira.py +++ b/miasm/arch/arm/ira.py @@ -7,19 +7,19 @@ from miasm.expression.expression import ExprAssign, ExprOp, ExprLoc, ExprCond from miasm.ir.ir import AssignBlock class ir_a_arml_base(ir_arml, ira): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_arml.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 class ir_a_armb_base(ir_armb, ira): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_armb.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 class ir_a_arml(ir_a_arml_base): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_a_arml_base.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 @@ -90,17 +90,17 @@ class ir_a_arml(ir_a_arml_base): class ir_a_armb(ir_a_armb_base, ir_a_arml): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_a_armb_base.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 class ir_a_armtl(ir_armtl, ir_a_arml): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_armtl.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 class ir_a_armtb(ir_a_armtl, ir_armtb, ir_a_armb): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_armtb.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 diff --git a/miasm/arch/arm/sem.py b/miasm/arch/arm/sem.py index 1884abe8..fd82df23 100644 --- a/miasm/arch/arm/sem.py +++ b/miasm/arch/arm/sem.py @@ -1933,7 +1933,7 @@ class arminfo(object): class ir_arml(IntermediateRepresentation): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_arm, "l", loc_db) self.pc = PC self.sp = SP @@ -2130,7 +2130,7 @@ class ir_arml(IntermediateRepresentation): class ir_armb(ir_arml): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_arm, "b", loc_db) self.pc = PC self.sp = SP @@ -2139,7 +2139,7 @@ class ir_armb(ir_arml): class ir_armtl(ir_arml): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_armt, "l", loc_db) self.pc = PC self.sp = SP @@ -2165,7 +2165,7 @@ class ir_armtl(ir_arml): class ir_armtb(ir_armtl): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_armt, "b", loc_db) self.pc = PC self.sp = SP diff --git a/miasm/arch/mep/ira.py b/miasm/arch/mep/ira.py index 2de4b5ae..eac4f6e9 100644 --- a/miasm/arch/mep/ira.py +++ b/miasm/arch/mep/ira.py @@ -12,7 +12,7 @@ class ir_a_mepb(ir_mepb, ira): - it is mandatory for symbolic execution. """ - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_mepb.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 @@ -41,5 +41,5 @@ class ir_a_mepb(ir_mepb, ira): class ir_a_mepl(ir_mepl, ir_a_mepb): """MeP high level IR manipulations - Little Endian""" - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_a_mepb.__init__(self, loc_db) diff --git a/miasm/arch/mep/sem.py b/miasm/arch/mep/sem.py index df484ab5..dccfc20d 100644 --- a/miasm/arch/mep/sem.py +++ b/miasm/arch/mep/sem.py @@ -1146,7 +1146,7 @@ class ir_mepb(IntermediateRepresentation): addrsize = 32 - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_mep, "b", loc_db) self.pc = mn_mep.getpc() self.sp = mn_mep.getsp() @@ -1172,7 +1172,7 @@ class ir_mepb(IntermediateRepresentation): class ir_mepl(ir_mepb): """Toshiba MeP miasm IR - Little Endian""" - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_mep, "l", loc_db) self.pc = mn_mep.getpc() self.sp = mn_mep.getsp() diff --git a/miasm/arch/mips32/ira.py b/miasm/arch/mips32/ira.py index e7b5d7f2..e57e3a36 100644 --- a/miasm/arch/mips32/ira.py +++ b/miasm/arch/mips32/ira.py @@ -6,7 +6,7 @@ from miasm.ir.analysis import ira from miasm.arch.mips32.sem import ir_mips32l, ir_mips32b class ir_a_mips32l(ir_mips32l, ira): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_mips32l.__init__(self, loc_db) self.ret_reg = self.arch.regs.V0 @@ -99,6 +99,6 @@ class ir_a_mips32l(ir_mips32l, ira): class ir_a_mips32b(ir_mips32b, ir_a_mips32l): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_mips32b.__init__(self, loc_db) self.ret_reg = self.arch.regs.V0 diff --git a/miasm/arch/mips32/sem.py b/miasm/arch/mips32/sem.py index b4252486..20ef007a 100644 --- a/miasm/arch/mips32/sem.py +++ b/miasm/arch/mips32/sem.py @@ -608,7 +608,7 @@ def get_mnemo_expr(ir, instr, *args): class ir_mips32l(IntermediateRepresentation): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_mips32, 'l', loc_db) self.pc = mn_mips32.getpc() self.sp = mn_mips32.getsp() @@ -641,7 +641,7 @@ class ir_mips32l(IntermediateRepresentation): return self.loc_db.get_or_create_offset_location(instr.offset + 16) class ir_mips32b(ir_mips32l): - def __init__(self, loc_db=None): + def __init__(self, loc_db): self.addrsize = 32 IntermediateRepresentation.__init__(self, mn_mips32, 'b', loc_db) self.pc = mn_mips32.getpc() diff --git a/miasm/arch/msp430/ira.py b/miasm/arch/msp430/ira.py index 72889149..264de12c 100644 --- a/miasm/arch/msp430/ira.py +++ b/miasm/arch/msp430/ira.py @@ -7,7 +7,7 @@ from miasm.expression.expression import * class ir_a_msp430_base(ir_msp430, ira): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_msp430.__init__(self, loc_db) self.ret_reg = self.arch.regs.R15 @@ -23,7 +23,7 @@ class ir_a_msp430_base(ir_msp430, ira): class ir_a_msp430(ir_a_msp430_base): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_a_msp430_base.__init__(self, loc_db) def get_out_regs(self, _): diff --git a/miasm/arch/msp430/sem.py b/miasm/arch/msp430/sem.py index 68605ae4..196e09f1 100644 --- a/miasm/arch/msp430/sem.py +++ b/miasm/arch/msp430/sem.py @@ -475,7 +475,7 @@ def ComposeExprAssign(dst, src): class ir_msp430(IntermediateRepresentation): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_msp430, None, loc_db) self.pc = PC self.sp = SP diff --git a/miasm/arch/ppc/ira.py b/miasm/arch/ppc/ira.py index 953c5a86..72bf7d7c 100644 --- a/miasm/arch/ppc/ira.py +++ b/miasm/arch/ppc/ira.py @@ -6,8 +6,8 @@ from miasm.arch.ppc.sem import ir_ppc32b class ir_a_ppc32b(ir_ppc32b, ira): - def __init__(self, *args): - super(ir_a_ppc32b, self).__init__(*args) + def __init__(self, loc_db, *args): + super(ir_a_ppc32b, self).__init__(loc_db, *args) self.ret_reg = self.arch.regs.R3 # for test XXX TODO diff --git a/miasm/arch/ppc/sem.py b/miasm/arch/ppc/sem.py index 26b3d84b..b05348f7 100644 --- a/miasm/arch/ppc/sem.py +++ b/miasm/arch/ppc/sem.py @@ -899,7 +899,7 @@ sem_dir = { class ir_ppc32b(IntermediateRepresentation): - def __init__(self, loc_db=None): + def __init__(self, loc_db): super(ir_ppc32b, self).__init__(mn_ppc, 'b', loc_db) self.pc = mn_ppc.getpc() self.sp = mn_ppc.getsp() diff --git a/miasm/arch/x86/ira.py b/miasm/arch/x86/ira.py index dc6db273..1615622b 100644 --- a/miasm/arch/x86/ira.py +++ b/miasm/arch/x86/ira.py @@ -8,7 +8,7 @@ from miasm.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 class ir_a_x86_16(ir_x86_16, ira): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_x86_16.__init__(self, loc_db) self.ret_reg = self.arch.regs.AX @@ -17,7 +17,7 @@ class ir_a_x86_16(ir_x86_16, ira): class ir_a_x86_32(ir_x86_32, ir_a_x86_16): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_x86_32.__init__(self, loc_db) self.ret_reg = self.arch.regs.EAX @@ -39,7 +39,7 @@ class ir_a_x86_32(ir_x86_32, ir_a_x86_16): class ir_a_x86_64(ir_x86_64, ir_a_x86_16): - def __init__(self, loc_db=None): + def __init__(self, loc_db): ir_x86_64.__init__(self, loc_db) self.ret_reg = self.arch.regs.RAX diff --git a/miasm/arch/x86/sem.py b/miasm/arch/x86/sem.py index 723272d5..6e593f51 100644 --- a/miasm/arch/x86/sem.py +++ b/miasm/arch/x86/sem.py @@ -5733,7 +5733,7 @@ mnemo_func = {'mov': mov, class ir_x86_16(IntermediateRepresentation): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_x86, 16, loc_db) self.do_stk_segm = False self.do_ds_segm = False @@ -5876,7 +5876,7 @@ class ir_x86_16(IntermediateRepresentation): class ir_x86_32(ir_x86_16): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_x86, 32, loc_db) self.do_stk_segm = False self.do_ds_segm = False @@ -5890,7 +5890,7 @@ class ir_x86_32(ir_x86_16): class ir_x86_64(ir_x86_16): - def __init__(self, loc_db=None): + def __init__(self, loc_db): IntermediateRepresentation.__init__(self, mn_x86, 64, loc_db) self.do_stk_segm = False self.do_ds_segm = False diff --git a/miasm/core/asmblock.py b/miasm/core/asmblock.py index e293ffda..47bffb34 100644 --- a/miasm/core/asmblock.py +++ b/miasm/core/asmblock.py @@ -91,22 +91,19 @@ class AsmBlock(object): loc_key = property(lambda self:self._loc_key) - def to_string(self, loc_db=None): + def to_string(self): out = [] - if loc_db is None: - out.append(str(self.loc_key)) - else: - out.append(loc_db.pretty_str(self.loc_key)) + out.append(self.loc_db.pretty_str(self.loc_key)) for instr in self.lines: - out.append(instr.to_string(loc_db)) + out.append(instr.to_string(self.loc_db)) if self.bto: lbls = ["->"] for dst in self.bto: if dst is None: lbls.append("Unknown? ") else: - lbls.append(dst.to_string(loc_db) + " ") + lbls.append(dst.to_string(self.loc_db) + " ") lbls = '\t'.join(sorted(lbls)) out.append(lbls) return '\n'.join(out) @@ -121,18 +118,18 @@ class AsmBlock(object): assert isinstance(self.bto, set) self.bto.add(c) - def split(self, loc_db, offset): - loc_key = loc_db.get_or_create_offset_location(offset) + def split(self, offset): + loc_key = self.loc_db.get_or_create_offset_location(offset) log_asmblock.debug('split at %x', offset) offsets = [x.offset for x in self.lines] - offset = loc_db.get_location_offset(loc_key) + offset = self.loc_db.get_location_offset(loc_key) if offset not in offsets: log_asmblock.warning( 'cannot split block at %X ' % offset + 'middle instruction? default middle') offsets.sort() return None - new_block = AsmBlock(loc_db, loc_key) + new_block = AsmBlock(self.loc_db, loc_key) i = offsets.index(offset) self.lines, new_block.lines = self.lines[:i], self.lines[i:] @@ -444,10 +441,7 @@ class AsmCFG(DiGraph): def node2lines(self, node): - if self.loc_db is None: - loc_key_name = node - else: - loc_key_name = self.loc_db.pretty_str(node) + loc_key_name = self.loc_db.pretty_str(node) yield self.DotCellDescription(text=loc_key_name, attr={'align': 'center', 'colspan': 2, @@ -903,7 +897,7 @@ class BlockChainWedge(object): return [self, chain] -def group_constrained_blocks(loc_db, asmcfg): +def group_constrained_blocks(asmcfg): """ Return the BlockChains list built from grouped blocks in asmcfg linked by asm_constraint_next @@ -942,7 +936,7 @@ def group_constrained_blocks(loc_db, asmcfg): out_block_chains = [] for loc_key in known_block_chains: - chain = BlockChain(loc_db, known_block_chains[loc_key]) + chain = BlockChain(asmcfg.loc_db, known_block_chains[loc_key]) out_block_chains.append(chain) return out_block_chains @@ -1023,8 +1017,8 @@ def get_block_loc_keys(block): return symbols -def assemble_block(mnemo, block, loc_db, conservative=False): - """Assemble a @block using @loc_db +def assemble_block(mnemo, block, conservative=False): + """Assemble a @block @conservative: (optional) use original bytes when possible """ offset_i = 0 @@ -1035,7 +1029,7 @@ def assemble_block(mnemo, block, loc_db, conservative=False): # Fix special AsmRaw data = b"" for expr in instr.raw: - expr_int = fix_expr_val(expr, loc_db) + expr_int = fix_expr_val(expr, block.loc_db) data += pck[expr_int.size](int(expr_int)) instr.data = data @@ -1045,17 +1039,17 @@ def assemble_block(mnemo, block, loc_db, conservative=False): # Assemble an instruction saved_args = list(instr.args) - instr.offset = loc_db.get_location_offset(block.loc_key) + offset_i + instr.offset = block.loc_db.get_location_offset(block.loc_key) + offset_i # Replace instruction's arguments by resolved ones - instr.args = instr.resolve_args_with_symbols(loc_db) + instr.args = instr.resolve_args_with_symbols(block.loc_db) if instr.dstflow(): instr.fixDstOffset() old_l = instr.l cached_candidate, _ = conservative_asm( - mnemo, instr, loc_db, + mnemo, instr, block.loc_db, conservative ) if len(cached_candidate) != instr.l: @@ -1063,11 +1057,11 @@ def assemble_block(mnemo, block, loc_db, conservative=False): # Retry assembly with updated length instr.l = len(cached_candidate) instr.args = saved_args - instr.args = instr.resolve_args_with_symbols(loc_db) + instr.args = instr.resolve_args_with_symbols(block.loc_db) if instr.dstflow(): instr.fixDstOffset() cached_candidate, _ = conservative_asm( - mnemo, instr, loc_db, + mnemo, instr, block.loc_db, conservative ) assert len(cached_candidate) == instr.l @@ -1083,8 +1077,8 @@ def assemble_block(mnemo, block, loc_db, conservative=False): offset_i += instr.l -def asmblock_final(mnemo, asmcfg, blockChains, loc_db, conservative=False): - """Resolve and assemble @blockChains using @loc_db until fixed point is +def asmblock_final(mnemo, asmcfg, blockChains, conservative=False): + """Resolve and assemble @blockChains until fixed point is reached""" log_asmblock.debug("asmbloc_final") @@ -1131,29 +1125,24 @@ def asmblock_final(mnemo, asmcfg, blockChains, loc_db, conservative=False): while blocks_to_rework: block = blocks_to_rework.pop() - assemble_block(mnemo, block, loc_db, conservative) + assemble_block(mnemo, block, conservative) -def asm_resolve_final(mnemo, asmcfg, loc_db, dst_interval=None): - """Resolve and assemble @asmcfg using @loc_db into interval +def asm_resolve_final(mnemo, asmcfg, dst_interval=None): + """Resolve and assemble @asmcfg into interval @dst_interval""" asmcfg.sanity_check() asmcfg.guess_blocks_size(mnemo) - blockChains = group_constrained_blocks(loc_db, asmcfg) - resolved_blockChains = resolve_symbol( - blockChains, - loc_db, - dst_interval - ) - - asmblock_final(mnemo, asmcfg, resolved_blockChains, loc_db) + blockChains = group_constrained_blocks(asmcfg) + resolved_blockChains = resolve_symbol(blockChains, asmcfg.loc_db, dst_interval) + asmblock_final(mnemo, asmcfg, resolved_blockChains) patches = {} output_interval = interval() for block in asmcfg.blocks: - offset = loc_db.get_location_offset(block.loc_key) + offset = asmcfg.loc_db.get_location_offset(block.loc_key) for instr in block.lines: if not instr.data: # Empty line @@ -1429,7 +1418,7 @@ class disasmEngine(object): # `cur_block` must be split at offset `off`from miasm.core.locationdb import LocationDB - new_b = cur_block.split(self.loc_db, off) + new_b = cur_block.split(off) log_asmblock.debug("Split block %x", off) if new_b is None: log_asmblock.error("Cannot split %x!!", off) diff --git a/miasm/ir/ir.py b/miasm/ir/ir.py index 00c73d09..aa04c54f 100644 --- a/miasm/ir/ir.py +++ b/miasm/ir/ir.py @@ -426,15 +426,21 @@ class IRBlock(object): self.cache_dst() return self._dst_linenb - def __str__(self): + def to_string(self): out = [] - out.append(str(self.loc_key)) + names = self.loc_db.get_location_names(self.loc_key) + if not names: + node_name = "%s:" % self.loc_db.pretty_str(self.loc_key) + else: + node_name = "".join("%s:\n" % name for name in names) + out.append(node_name) + for assignblk in self: - for dst, src in viewitems(assignblk): - out.append('\t%s = %s' % (dst, src)) - out.append("") - return "\n".join(out) + out.append(assignblk.to_string(self.loc_db)) + return '\n'.join(out) + def __str__(self): + return self.to_string() def modify_exprs(self, mod_dst=None, mod_src=None): """ @@ -457,23 +463,6 @@ class IRBlock(object): assignblks.append(AssignBlock(new_assignblk, assignblk.instr)) return IRBlock(self.loc_db, self.loc_key, assignblks) - def to_string(self, loc_db=None): - out = [] - if loc_db is None: - node_name = "%s:" % self.loc_key - else: - names = loc_db.get_location_names(self.loc_key) - if not names: - node_name = "%s:" % loc_db.pretty_str(self.loc_key) - else: - node_name = "".join("%s:\n" % name for name in names) - out.append(node_name) - - for assignblk in self: - out.append(assignblk.to_string(loc_db)) - return '\n'.join(out) - - def simplify(self, simplifier): """ Simplify expressions in each assignblock @@ -540,10 +529,7 @@ class IRCFG(DiGraph): self.add_uniq_edge(irblock.loc_key, dst.loc_key) def node2lines(self, node): - if self.loc_db is None: - node_name = str(node) - else: - node_name = self.loc_db.pretty_str(node) + node_name = self.loc_db.pretty_str(node) yield self.DotCellDescription( text="%s" % node_name, attr={ diff --git a/miasm/jitter/jitcore.py b/miasm/jitter/jitcore.py index cc531cf5..a6c9dda6 100644 --- a/miasm/jitter/jitcore.py +++ b/miasm/jitter/jitcore.py @@ -144,7 +144,7 @@ class JitCore(object): return cur_block # Logging if self.log_newbloc: - print(cur_block.to_string(self.mdis.loc_db)) + print(cur_block) # Update label -> block self.loc_key_to_block[cur_block.loc_key] = cur_block diff --git a/test/analysis/data_flow.py b/test/analysis/data_flow.py index 47d521bc..840bf9ce 100644 --- a/test/analysis/data_flow.py +++ b/test/analysis/data_flow.py @@ -72,7 +72,7 @@ class IRATest(ira): """Fake IRA class for tests""" - def __init__(self, loc_db=None): + def __init__(self, loc_db): arch = Arch() super(IRATest, self).__init__(arch, 32, loc_db) self.IRDst = IRDst diff --git a/test/analysis/depgraph.py b/test/analysis/depgraph.py index a458e533..49a395a1 100644 --- a/test/analysis/depgraph.py +++ b/test/analysis/depgraph.py @@ -95,7 +95,7 @@ class IRATest(ira): """Fake IRA class for tests""" - def __init__(self, loc_db=None): + def __init__(self, loc_db): arch = Arch() super(IRATest, self).__init__(arch, 32, loc_db) self.IRDst = ExprId("IRDst", 32) diff --git a/test/analysis/dse.py b/test/analysis/dse.py index cd813d2c..570860e4 100644 --- a/test/analysis/dse.py +++ b/test/analysis/dse.py @@ -73,7 +73,7 @@ class DSETest(object): def asm(self): mn_x86 = self.machine.mn - blocks = parse_asm.parse_txt( + asmcfg = parse_asm.parse_txt( mn_x86, self.arch_attrib, self.TXT, @@ -83,7 +83,7 @@ class DSETest(object): # fix shellcode addr self.loc_db.set_location_offset(self.loc_db.get_name_location("main"), 0x0) output = StrPatchwork() - patches = asm_resolve_final(mn_x86, blocks, self.loc_db) + patches = asm_resolve_final(mn_x86, asmcfg) for offset, raw in viewitems(patches): output[offset] = raw @@ -117,7 +117,7 @@ class DSEAttachInBreakpoint(DSETest): super(DSEAttachInBreakpoint, self).__init__(*args, **kwargs) self._dse = None ircls = self.machine.ir - self._regs = ircls().arch.regs + self._regs = ircls(self.loc_db).arch.regs self._testid = ExprId("TEST", self._regs.EBX.size) def bp_attach(self, jitter): diff --git a/test/arch/aarch64/unit/asm_test.py b/test/arch/aarch64/unit/asm_test.py index d6ed5223..d9a484b7 100644 --- a/test/arch/aarch64/unit/asm_test.py +++ b/test/arch/aarch64/unit/asm_test.py @@ -26,11 +26,11 @@ class Asm_Test(object): self.check() def asm(self): - blocks = parse_asm.parse_txt(mn_aarch64, 'l', self.TXT, self.loc_db) + asmcfg = parse_asm.parse_txt(mn_aarch64, 'l', self.TXT, self.loc_db) # fix shellcode addr self.loc_db.set_location_offset(self.loc_db.get_name_location("main"), 0x0) s = StrPatchwork() - patches = asmblock.asm_resolve_final(mn_aarch64, blocks, self.loc_db) + patches = asmblock.asm_resolve_final(mn_aarch64, asmcfg) for offset, raw in viewitems(patches): s[offset] = raw diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py index f38d48e9..49d46a4d 100755 --- a/test/arch/arm/sem.py +++ b/test/arch/arm/sem.py @@ -16,7 +16,8 @@ from miasm.core.locationdb import LocationDB from pdb import pm logging.getLogger('cpuhelper').setLevel(logging.ERROR) -EXCLUDE_REGS = set([ir_arch().IRDst]) +loc_db = LocationDB() +EXCLUDE_REGS = set([ir_arch(loc_db).IRDst]) def M(addr): diff --git a/test/arch/mep/ir/test_ir.py b/test/arch/mep/ir/test_ir.py index be8e24e1..97a3ec1e 100644 --- a/test/arch/mep/ir/test_ir.py +++ b/test/arch/mep/ir/test_ir.py @@ -27,13 +27,14 @@ class TestMisc(object): mn = mn_mep.dis(decode_hex(hex_asm), "b") print("Dis:", mn) + loc_db = LocationDB() + # Get the IR - im = ir_mepb() + im = ir_mepb(loc_db) iir, eiir, = im.get_ir(mn) print("\nInternal representation:", iir) # Symbolic execution - loc_db = LocationDB() sb = SymbolicExecutionEngine(ir_a_mepb(loc_db), regs_init) # Assign register values before symbolic evaluation diff --git a/test/arch/mips32/unit/asm_test.py b/test/arch/mips32/unit/asm_test.py index 164cc143..d6194b00 100644 --- a/test/arch/mips32/unit/asm_test.py +++ b/test/arch/mips32/unit/asm_test.py @@ -28,11 +28,11 @@ class Asm_Test(object): self.check() def asm(self): - blocks = parse_asm.parse_txt(mn_mips32, 'l', self.TXT, self.loc_db) + asmcfg = parse_asm.parse_txt(mn_mips32, 'l', self.TXT, self.loc_db) # fix shellcode addr self.loc_db.set_location_offset(self.loc_db.get_name_location("main"), 0x0) s = StrPatchwork() - patches = asmblock.asm_resolve_final(mn_mips32, blocks, self.loc_db) + patches = asmblock.asm_resolve_final(mn_mips32, asmcfg) for offset, raw in viewitems(patches): s[offset] = raw diff --git a/test/arch/msp430/sem.py b/test/arch/msp430/sem.py index cb101937..2b3c4afe 100755 --- a/test/arch/msp430/sem.py +++ b/test/arch/msp430/sem.py @@ -15,7 +15,8 @@ from miasm.expression.expression import * from miasm.core.locationdb import LocationDB logging.getLogger('cpuhelper').setLevel(logging.ERROR) -EXCLUDE_REGS = set([res, ir_arch().IRDst]) +loc_db = LocationDB() +EXCLUDE_REGS = set([res, ir_arch(loc_db).IRDst]) def M(addr): diff --git a/test/arch/ppc32/sem.py b/test/arch/ppc32/sem.py index 95ef08c8..53c93369 100644 --- a/test/arch/ppc32/sem.py +++ b/test/arch/ppc32/sem.py @@ -16,7 +16,8 @@ from miasm.core.locationdb import LocationDB from pdb import pm logging.getLogger('cpuhelper').setLevel(logging.ERROR) -EXCLUDE_REGS = set([ir_arch().IRDst]) +loc_db = LocationDB() +EXCLUDE_REGS = set([ir_arch(loc_db).IRDst]) def M(addr): diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py index 3d40d44c..9c7e972b 100755 --- a/test/arch/x86/sem.py +++ b/test/arch/x86/sem.py @@ -21,9 +21,9 @@ from miasm.expression.simplifications import expr_simp from miasm.core import parse_asm, asmblock from miasm.core.locationdb import LocationDB - logging.getLogger('cpuhelper').setLevel(logging.ERROR) -EXCLUDE_REGS = set([ir_32().IRDst, ir_64().IRDst]) +loc_db = LocationDB() +EXCLUDE_REGS = set([ir_32(loc_db).IRDst, ir_64(loc_db).IRDst]) m32 = 32 @@ -59,7 +59,7 @@ def compute_txt(ir, mode, txt, inputstate={}, debug=False): loc_db = LocationDB() asmcfg = parse_asm.parse_txt(mn, mode, txt, loc_db) loc_db.set_location_offset(loc_db.get_name_location("main"), 0x0) - patches = asmblock.asm_resolve_final(mn, asmcfg, loc_db) + patches = asmblock.asm_resolve_final(mn, asmcfg) ir_arch = ir(loc_db) lbl = loc_db.get_name_location("main") ircfg = ir_arch.new_ircfg_from_asmcfg(asmcfg) diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py index d3ecf660..62923310 100644 --- a/test/arch/x86/unit/asm_test.py +++ b/test/arch/x86/unit/asm_test.py @@ -45,11 +45,11 @@ class Asm_Test(object): assert(self.myjit.pc == self.ret_addr) def asm(self): - blocks = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT, self.loc_db) + asmcfg = parse_asm.parse_txt(mn_x86, self.arch_attrib, self.TXT, self.loc_db) # fix shellcode addr self.loc_db.set_location_offset(self.loc_db.get_name_location("main"), 0x0) s = StrPatchwork() - patches = asmblock.asm_resolve_final(mn_x86, blocks, self.loc_db) + patches = asmblock.asm_resolve_final(mn_x86, asmcfg) for offset, raw in viewitems(patches): s[offset] = raw diff --git a/test/arch/x86/unit/test_asm_x86_64.py b/test/arch/x86/unit/test_asm_x86_64.py index e1d99ec1..f56770dc 100644 --- a/test/arch/x86/unit/test_asm_x86_64.py +++ b/test/arch/x86/unit/test_asm_x86_64.py @@ -29,6 +29,5 @@ dst_interval = interval([(0x100001000, 0x100002000)]) patches = asmblock.asm_resolve_final( my_mn, asmcfg, - loc_db, dst_interval ) diff --git a/test/core/parse_asm.py b/test/core/parse_asm.py index fdf1fbb8..5619f5c1 100755 --- a/test/core/parse_asm.py +++ b/test/core/parse_asm.py @@ -69,7 +69,7 @@ class TestParseAsm(unittest.TestCase): ''' asmcfg = parse_txt(mn_x86, 32, ASM0, loc_db) - patches = asm_resolve_final(mn_x86, asmcfg, loc_db) + patches = asm_resolve_final(mn_x86, asmcfg) lbls = [] for i in range(6): lbls.append(loc_db.get_name_location('lbl%d' % i)) diff --git a/test/ir/reduce_graph.py b/test/ir/reduce_graph.py index 73af4860..4aa2d5ef 100644 --- a/test/ir/reduce_graph.py +++ b/test/ir/reduce_graph.py @@ -74,7 +74,7 @@ class IRATest(ira): """Fake IRA class for tests""" - def __init__(self, loc_db=None): + def __init__(self, loc_db): arch = Arch() super(IRATest, self).__init__(arch, 32, loc_db) self.IRDst = IRDst |