diff options
| -rw-r--r-- | miasm2/arch/arm/sem.py | 9 | ||||
| -rw-r--r-- | miasm2/arch/msp430/sem.py | 5 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 31 |
3 files changed, 25 insertions, 20 deletions
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index 06f6bddf..2261fb3f 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -1191,10 +1191,11 @@ class ir_arml(ir): if args[-1].op == 'rrx': args[-1] = ExprCompose( [(args[-1].args[0][1:], 0, 31), (cf, 31, 32)]) - elif (args[-1].op in ['<<', '>>', '<<a', 'a>>', '<<<', '>>>'] and - isinstance(args[-1].args[-1], ExprId)): - args[-1].args = args[-1].args[:-1] + ( - args[-1].args[-1][:8].zeroExtend(32),) + elif args[-1].op in ['<<', '>>', '<<a', 'a>>', '<<<', '>>>']: + if isinstance(args[-1].args[-1], ExprId): + args[-1] = ExprOp(args[-1].op, + args[-1].args[0], + args[-1].args[-1][:8].zeroExtend(32)) instr_ir, extra_ir = get_mnemo_expr(self, instr, *args) # if self.name.startswith('B'): # return instr_ir, extra_ir diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py index ac4c7e9c..cec8f36f 100644 --- a/miasm2/arch/msp430/sem.py +++ b/miasm2/arch/msp430/sem.py @@ -432,11 +432,12 @@ class ir_msp430(ir): def mod_sr(self, instr, instr_ir, extra_ir): for i, x in enumerate(instr_ir): - x.src = x.src.replace_expr({SR: composed_sr}) + x = ExprAff(x.dst, x.src.replace_expr({SR: composed_sr})) + instr_ir[i] = x if x.dst != SR: continue xx = ComposeExprAff(composed_sr, x.src) - instr_ir[i:i + 1] = xx + instr_ir[i] = xx for i, x in enumerate(instr_ir): x = ExprAff(x.dst, x.src.replace_expr( {self.pc: ExprInt16(instr.offset + instr.l)})) diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 52cec344..50cb8f05 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -3515,8 +3515,9 @@ class ir_x86_16(ir): for b in extra_ir: for ir in b.irs: - for e in ir: - e.src = e.src.replace_expr({lbl_next: lbl_end}) + for i, e in enumerate(ir): + src = e.src.replace_expr({lbl_next: lbl_end}) + ir[i] = m2_expr.ExprAff(e.dst, src) cond_bloc = [] cond_bloc.append(m2_expr.ExprAff(c_reg, c_reg - m2_expr.ExprInt_from(c_reg, @@ -3586,19 +3587,21 @@ class ir_x86_64(ir_x86_16): def mod_pc(self, instr, instr_ir, extra_ir): # fix RIP for 64 bit - for i, x in enumerate(instr_ir): - if x.dst != self.pc: - x.dst = x.dst.replace_expr( + for i, expr in enumerate(instr_ir): + dst, src = expr.dst, expr.src + if dst != self.pc: + dst = dst.replace_expr( {self.pc: m2_expr.ExprInt64(instr.offset + instr.l)}) - x = m2_expr.ExprAff(x.dst, x.src.replace_expr( - {self.pc: m2_expr.ExprInt64(instr.offset + instr.l)})) - instr_ir[i] = x + src = src.replace_expr( + {self.pc: m2_expr.ExprInt64(instr.offset + instr.l)}) + instr_ir[i] = m2_expr.ExprAff(dst, src) for b in extra_ir: for irs in b.irs: - for i, x in enumerate(irs): - if x.dst != self.pc: + for i, expr in enumerate(irs): + dst, src = expr.dst, expr.src + if dst != self.pc: new_pc = m2_expr.ExprInt64(instr.offset + instr.l) - x.dst = x.dst.replace_expr({self.pc: new_pc}) - x = m2_expr.ExprAff(x.dst, x.src.replace_expr( - {self.pc: m2_expr.ExprInt64(instr.offset + instr.l)})) - irs[i] = x + dst = dst.replace_expr({self.pc: new_pc}) + src = src.replace_expr( + {self.pc: m2_expr.ExprInt64(instr.offset + instr.l)}) + irs[i] = m2_expr.ExprAff(dst, src) |