diff options
67 files changed, 621 insertions, 558 deletions
diff --git a/README.md b/README.md index fa76a694..bea3d943 100644 --- a/README.md +++ b/README.md @@ -111,15 +111,15 @@ ADD R2, R8, R0 Create an intermediate representation object: ```pycon ->>> ira = machine.ira(loc_db) +>>> lifter = machine.lifter_model_call(loc_db) ``` Create an empty ircfg ```pycon ->>> ircfg = ira.new_ircfg() +>>> ircfg = lifter.new_ircfg() ``` Add instruction to the pool: ```pycon ->>> ira.add_instr_to_ircfg(instr, ircfg) +>>> lifter.add_instr_to_ircfg(instr, ircfg) ``` Print current pool: @@ -284,15 +284,15 @@ Symbolic execution Initializing the IR pool: ```pycon ->>> ira = machine.ira(loc_db) ->>> ircfg = ira.new_ircfg_from_asmcfg(asmcfg) +>>> lifter = machine.lifter_model_call(loc_db) +>>> ircfg = lifter.new_ircfg_from_asmcfg(asmcfg) ``` Initializing the engine with default symbolic values: ```pycon >>> from miasm.ir.symbexec import SymbolicExecutionEngine ->>> sb = SymbolicExecutionEngine(ira) +>>> sb = SymbolicExecutionEngine(lifter) ``` Launching the execution: @@ -306,7 +306,7 @@ Launching the execution: Same, with step logs (only changes are displayed): ```pycon ->>> sb = SymbolicExecutionEngine(ira, machine.mn.regs.regs_init) +>>> sb = SymbolicExecutionEngine(lifter, machine.mn.regs.regs_init) >>> symbolic_pc = sb.run_at(ircfg, 0, step=True) Instr LEA ECX, DWORD PTR [ECX + 0x4] Assignblk: diff --git a/doc/ir/lift.ipynb b/doc/ir/lift.ipynb index 08d4dde6..aaa20a0b 100644 --- a/doc/ir/lift.ipynb +++ b/doc/ir/lift.ipynb @@ -33,7 +33,7 @@ "from miasm.analysis.machine import Machine\n", "from miasm.arch.x86.arch import mn_x86\n", "from miasm.core import parse_asm, asmblock\n", - "from miasm.arch.x86.ira import ir_a_x86_32\n", + "from miasm.arch.x86.lifter_model_call import LifterModelCall_x86_32\n", "from miasm.core.locationdb import LocationDB\n", "from miasm.loader.strpatchwork import StrPatchwork\n", "from miasm.analysis.binary import Container\n", @@ -82,23 +82,23 @@ " asmcfg = mdis.dis_multiblock(0)\n", " return asmcfg\n", "\n", - "def lift_x86_asm(asm, ira=False, ira_custom=None):\n", + "def lift_x86_asm(asm, model_call=False, lifter_custom=None):\n", " asmcfg = gen_x86_asmcfg(asm)\n", " machine = Machine(\"x86_32\")\n", " # Get a lifter\n", - " if ira and ira_custom is None:\n", - " ir_arch = ir_a_x86_32(asmcfg.loc_db)\n", - " elif ira_custom is not None:\n", - " ir_arch = ira_custom(asmcfg.loc_db)\n", + " if model_call and lifter_custom is None:\n", + " lifter = LifterModelCall_x86_32(asmcfg.loc_db)\n", + " elif lifter_custom is not None:\n", + " lifter = lifter_custom(asmcfg.loc_db)\n", " else:\n", - " ir_arch = machine.ir(asmcfg.loc_db)\n", + " lifter = machine.lifter(asmcfg.loc_db)\n", "\n", " # Translate to IR\n", - " ircfg = ir_arch.new_ircfg_from_asmcfg(asmcfg)\n", + " ircfg = lifter.new_ircfg_from_asmcfg(asmcfg)\n", " return ircfg\n", "\n", - "def graph_ir_x86(asm, ira=False, ira_custom=None):\n", - " ircfg = lift_x86_asm(asm, ira, ira_custom)\n", + "def graph_ir_x86(asm, model_call=False, lifter_custom=None):\n", + " ircfg = lift_x86_asm(asm, model_call, lifter_custom)\n", " return ircfg.graphviz()\n" ] }, @@ -147,7 +147,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c460340>" + "<graphviz.dot.Digraph at 0x7f62910602b0>" ] }, "execution_count": 2, @@ -211,7 +211,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fada42cb7f0>" + "<graphviz.dot.Digraph at 0x7f6291002a30>" ] }, "execution_count": 3, @@ -296,7 +296,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c457520>" + "<graphviz.dot.Digraph at 0x7f62a0172970>" ] }, "execution_count": 4, @@ -382,7 +382,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c44af40>" + "<graphviz.dot.Digraph at 0x7f6290fc1910>" ] }, "execution_count": 5, @@ -483,7 +483,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c4020d0>" + "<graphviz.dot.Digraph at 0x7f6290fc16d0>" ] }, "execution_count": 6, @@ -566,7 +566,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c460100>" + "<graphviz.dot.Digraph at 0x7f629102b250>" ] }, "execution_count": 7, @@ -662,7 +662,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c3ce970>" + "<graphviz.dot.Digraph at 0x7f6290fd6100>" ] }, "execution_count": 8, @@ -778,7 +778,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c40f190>" + "<graphviz.dot.Digraph at 0x7f629103a1f0>" ] }, "execution_count": 9, @@ -926,7 +926,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c41fc70>" + "<graphviz.dot.Digraph at 0x7f6290fe18b0>" ] }, "execution_count": 10, @@ -1007,7 +1007,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c41f3a0>" + "<graphviz.dot.Digraph at 0x7f6290fd6df0>" ] }, "execution_count": 11, @@ -1101,7 +1101,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c3e2820>" + "<graphviz.dot.Digraph at 0x7f62a01729d0>" ] }, "execution_count": 12, @@ -1213,7 +1213,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c44a400>" + "<graphviz.dot.Digraph at 0x7f6290fc7d90>" ] }, "execution_count": 13, @@ -1287,7 +1287,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c474520>" + "<graphviz.dot.Digraph at 0x7f629106a640>" ] }, "execution_count": 14, @@ -1356,7 +1356,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c4029a0>" + "<graphviz.dot.Digraph at 0x7f629106ab80>" ] }, "execution_count": 15, @@ -1451,7 +1451,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fada46612b0>" + "<graphviz.dot.Digraph at 0x7f6291002940>" ] }, "execution_count": 16, @@ -1541,7 +1541,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c402b50>" + "<graphviz.dot.Digraph at 0x7f6290f66df0>" ] }, "execution_count": 17, @@ -1576,15 +1576,15 @@ "source": [ "This `raw` way of translating is interesting to see low level moves of stack and return address, but it makes code analysis a bit hard. What we may want is to consider subcalls like an unknown operator, with arguments and side effects. This may *model* the call to a subfunction.\n", "\n", - "This is the difference in Miasm between translating using `ir` (raw translation) and `ira` (`ir` + analysis) which models subfunction calls. By default, Miasm uses a basic model which is *wrong* in most cases. But this model can (and must ?) be replaced by the user behavior.\n", + "This is the difference in Miasm between translating using `lifter` (raw translation) and `lifter_model_call` (`ilifter` + call modelization) which models subfunction calls. By default, Miasm uses a basic model which is *wrong* in most cases. But this model can (and must ?) be replaced by the user behavior.\n", "\n", "You can observe the difference in the examples:\n", "```\n", - "example/disasm/dis_binary_ir.py\n", + "example/disasm/dis_binary_lift.py\n", "```\n", "and\n", "```\n", - "example/disasm/dis_binary_ira.py\n", + "example/disasm/dis_binary_lifter_model_call.py\n", "```\n" ] }, @@ -1639,7 +1639,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c3e2af0>" + "<graphviz.dot.Digraph at 0x7f6291012670>" ] }, "execution_count": 18, @@ -1675,7 +1675,7 @@ "metadata": {}, "source": [ "# Subfunction call custom modeling\n", - "The code responsible of the modelisation of function calls is located in the `ira` class (the lifter with call modeling) in `miasm/ir/analysis.py`:\n", + "The code responsible of the modelisation of function calls is located in the `LifterModelCall` class (the lifter with call modeling) in `miasm/ir/analysis.py`:\n", "```python\n", "...\n", " def call_effects(self, addr, instr):\n", @@ -1703,7 +1703,7 @@ "\n", "```\n", "\n", - "Some architectures subclass it to include some architecture dependent stuffs, for example in `miasm/arch/x86/ira.py` in which we use a default calling convention linked to arguments passed through registers:\n", + "Some architectures subclass it to include some architecture dependent stuffs, for example in `miasm/arch/x86/lifter_model_call.py` in which we use a default calling convention linked to arguments passed through registers:\n", "```python\n", "...\n", " def call_effects(self, ad, instr):\n", @@ -1792,7 +1792,7 @@ "</svg>\n" ], "text/plain": [ - "<graphviz.dot.Digraph at 0x7fad9c474d90>" + "<graphviz.dot.Digraph at 0x7f6290e9b940>" ] }, "execution_count": 19, @@ -1801,8 +1801,8 @@ } ], "source": [ - "# Construct a custom ira lifter\n", - "class IRAFixCallStack(ir_a_x86_32):\n", + "# Construct a custom lifter\n", + "class LifterFixCallStack(LifterModelCall_x86_32):\n", " def call_effects(self, addr, instr):\n", " if addr.is_loc():\n", " if self.loc_db.get_location_offset(addr.loc_key) == 0x11223344:\n", @@ -1837,7 +1837,7 @@ " CALL 0x11223344\n", " MOV ECX, EAX\n", " RET\n", - "\"\"\", ira_custom=IRAFixCallStack)" + "\"\"\", lifter_custom=LifterFixCallStack)" ] }, { @@ -1870,7 +1870,7 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.8.6" + "version": "3.9.0" } }, "nbformat": 4, diff --git a/doc/locationdb/locationdb.ipynb b/doc/locationdb/locationdb.ipynb index 4425b3ad..33a18930 100644 --- a/doc/locationdb/locationdb.ipynb +++ b/doc/locationdb/locationdb.ipynb @@ -396,7 +396,7 @@ "outputs": [], "source": [ "# Get a lifter\n", - "lifter = machine.ira(loc_db)" + "lifter = machine.lifter_model_call(loc_db)" ] }, { diff --git a/example/disasm/dis_binary_ir.py b/example/disasm/dis_binary_lift.py index 3facd74b..6ad69b05 100644 --- a/example/disasm/dis_binary_ir.py +++ b/example/disasm/dis_binary_lift.py @@ -25,8 +25,8 @@ asmcfg = mdis.dis_multiblock(addr) # End common section # ##################################### -# Get an IR converter -ir_arch = machine.ir(mdis.loc_db) +# Get a Lifter +ir_arch = machine.lifter(mdis.loc_db) # Get the IR of the asmcfg ircfg = ir_arch.new_ircfg_from_asmcfg(asmcfg) diff --git a/example/disasm/dis_binary_ira.py b/example/disasm/dis_binary_lift_model_call.py index bfed3497..95b3a70b 100644 --- a/example/disasm/dis_binary_ira.py +++ b/example/disasm/dis_binary_lift_model_call.py @@ -29,7 +29,7 @@ asmcfg = mdis.dis_multiblock(addr) # Get an IRA converter # The sub call are modelised by default operators # call_func_ret and call_func_stack -ir_arch_analysis = machine.ira(mdis.loc_db) +ir_arch_analysis = machine.lifter_model_call(mdis.loc_db) # Get the IR of the asmcfg ircfg_analysis = ir_arch_analysis.new_ircfg_from_asmcfg(asmcfg) @@ -39,4 +39,4 @@ for irblock in viewvalues(ircfg_analysis.blocks): print(irblock) # Output ir control flow graph in a dot file -open('bin_ira_cfg.dot', 'w').write(ircfg_analysis.dot()) +open('bin_lifter_model_call_cfg.dot', 'w').write(ircfg_analysis.dot()) diff --git a/example/disasm/full.py b/example/disasm/full.py index 47eca56d..3408e6d7 100644 --- a/example/disasm/full.py +++ b/example/disasm/full.py @@ -106,7 +106,6 @@ if not arch: # Instance the arch-dependent machine machine = Machine(arch) mn, dis_engine = machine.mn, machine.dis_engine -ira, ir = machine.ira, machine.ir log.info('ok') mdis = dis_engine(bs, loc_db=cont.loc_db) @@ -215,9 +214,9 @@ if args.propagexpr: args.gen_ir = True -class IRADelModCallStack(ira): +class LifterDelModCallStack(machine.lifter_model_call): def call_effects(self, addr, instr): - assignblks, extra = super(IRADelModCallStack, self).call_effects(addr, instr) + assignblks, extra = super(LifterDelModCallStack, self).call_effects(addr, instr) if not args.calldontmodstack: return assignblks, extra out = [] @@ -232,21 +231,21 @@ class IRADelModCallStack(ira): # Bonus, generate IR graph if args.gen_ir: - log.info("generating IR and IR analysis") + log.info("Lift and Lift with modeled calls") - ir_arch = ir(mdis.loc_db) - ir_arch_a = IRADelModCallStack(mdis.loc_db) + lifter = machine.lifter(mdis.loc_db) + lifter_model_call = LifterDelModCallStack(mdis.loc_db) - ircfg = ir_arch.new_ircfg() - ircfg_a = ir_arch.new_ircfg() + ircfg = lifter.new_ircfg() + ircfg_a = lifter.new_ircfg() head = list(entry_points)[0] for ad, asmcfg in viewitems(all_funcs_blocks): log.info("generating IR... %x" % ad) for block in asmcfg.blocks: - ir_arch.add_asmblock_to_ircfg(block, ircfg) - ir_arch_a.add_asmblock_to_ircfg(block, ircfg_a) + lifter.add_asmblock_to_ircfg(block, ircfg) + lifter_model_call.add_asmblock_to_ircfg(block, ircfg_a) log.info("Print blocks (without analyse)") for label, block in viewitems(ircfg.blocks): @@ -260,7 +259,7 @@ if args.gen_ir: if args.simplify > 0: log.info("Simplify...") - ircfg_simplifier = IRCFGSimplifierCommon(ir_arch_a) + ircfg_simplifier = IRCFGSimplifierCommon(lifter_model_call) ircfg_simplifier.simplify(ircfg_a, head) log.info("ok...") @@ -309,12 +308,12 @@ if args.propagexpr: ssa = self.do_simplify_loop(ssa, head) ircfg = self.ssa_to_unssa(ssa, head) - ircfg_simplifier = IRCFGSimplifierCommon(self.ir_arch) + ircfg_simplifier = IRCFGSimplifierCommon(self.lifter) ircfg_simplifier.deadremoval.add_expr_to_original_expr(ssa.ssa_variable_to_expr) ircfg_simplifier.simplify(ircfg, head) return ircfg head = list(entry_points)[0] - simplifier = CustomIRCFGSimplifierSSA(ir_arch_a) + simplifier = CustomIRCFGSimplifierSSA(lifter_model_call) ircfg = simplifier.simplify(ircfg_a, head) open('final.dot', 'w').write(ircfg.dot()) diff --git a/example/expression/access_c.py b/example/expression/access_c.py index 3cc8e6a2..fd50a917 100644 --- a/example/expression/access_c.py +++ b/example/expression/access_c.py @@ -95,10 +95,10 @@ class MyExprToAccessC(ExprToAccessC): reduction_rules = ExprToAccessC.reduction_rules + [reduce_compose] -def get_funcs_arg0(ctx, ira, ircfg, lbl_head): +def get_funcs_arg0(ctx, lifter_model_call, ircfg, lbl_head): """Compute DependencyGraph on the func @lbl_head""" g_dep = DependencyGraph(ircfg, follow_call=False) - element = ira.arch.regs.RSI + element = lifter_model_call.arch.regs.RSI for loc_key, index in find_call(ircfg): irb = ircfg.get_block(loc_key) @@ -106,7 +106,7 @@ def get_funcs_arg0(ctx, ira, ircfg, lbl_head): print('Analysing references from:', hex(instr.offset), instr) g_list = g_dep.get(irb.loc_key, set([element]), index, set([lbl_head])) for dep in g_list: - emul_result = dep.emul(ira, ctx) + emul_result = dep.emul(lifter_model_call, ctx) value = emul_result[element] yield value @@ -144,14 +144,14 @@ types_mngr = CTypesManagerNotPacked(types_ast, base_types) cont = Container.fallback_container(data, None, addr=0) machine = Machine("x86_64") -dis_engine, ira = machine.dis_engine, machine.ira +dis_engine, lifter_model_call = machine.dis_engine, machine.lifter_model_call mdis = dis_engine(cont.bin_stream, loc_db=loc_db) addr_head = 0 asmcfg = mdis.dis_multiblock(addr_head) lbl_head = loc_db.get_offset_location(addr_head) -ir_arch_a = ira(loc_db) +ir_arch_a = lifter_model_call(loc_db) ircfg = ir_arch_a.new_ircfg_from_asmcfg(asmcfg) open('graph_irflow.dot', 'w').write(ircfg.dot()) diff --git a/example/expression/asm_to_ir.py b/example/expression/asm_to_ir.py index 8ecc4f24..9be7d1b3 100644 --- a/example/expression/asm_to_ir.py +++ b/example/expression/asm_to_ir.py @@ -7,7 +7,7 @@ from miasm.arch.x86.arch import mn_x86 from miasm.core import parse_asm from miasm.expression.expression import * from miasm.core import asmblock -from miasm.arch.x86.ira import ir_a_x86_32 +from miasm.arch.x86.lifter_model_call import LifterModelCall_x86_32 from miasm.analysis.data_flow import DeadRemoval from miasm.core.locationdb import LocationDB @@ -43,7 +43,7 @@ print(loc_db) patches = asmblock.asm_resolve_final(mn_x86, asmcfg) # Translate to IR -ir_arch = ir_a_x86_32(loc_db) +ir_arch = LifterModelCall_x86_32(loc_db) ircfg = ir_arch.new_ircfg_from_asmcfg(asmcfg) deadrm = DeadRemoval(ir_arch) diff --git a/example/expression/constant_propagation.py b/example/expression/constant_propagation.py index a5929eed..0ea8028c 100644 --- a/example/expression/constant_propagation.py +++ b/example/expression/constant_propagation.py @@ -30,7 +30,7 @@ machine = Machine("x86_32") loc_db = LocationDB() cont = Container.from_stream(open(args.filename, 'rb'), loc_db) mdis = machine.dis_engine(cont.bin_stream, loc_db=loc_db) -ir_arch = machine.ira(mdis.loc_db) +ir_arch = machine.lifter_model_call(mdis.loc_db) addr = int(args.address, 0) deadrm = DeadRemoval(ir_arch) diff --git a/example/expression/export_llvm.py b/example/expression/export_llvm.py index a4c65787..74587ffd 100644 --- a/example/expression/export_llvm.py +++ b/example/expression/export_llvm.py @@ -17,16 +17,16 @@ loc_db = LocationDB() # This part focus on obtaining an IRCFG to transform # cont = Container.from_stream(open(args.target, 'rb'), loc_db) machine = Machine(args.architecture if args.architecture else cont.arch) -ir = machine.ir(loc_db) +lifter = machine.lifter(loc_db) dis = machine.dis_engine(cont.bin_stream, loc_db=loc_db) asmcfg = dis.dis_multiblock(int(args.addr, 0)) -ircfg = ir.new_ircfg_from_asmcfg(asmcfg) +ircfg = lifter.new_ircfg_from_asmcfg(asmcfg) ircfg.simplify(expr_simp_high_to_explicit) ###################################################### # Instantiate a context and the function to fill context = LLVMContext_IRCompilation() -context.ir_arch = ir +context.lifter = lifter func = LLVMFunction_IRCompilation(context, name="test") func.ret_type = llvm_ir.VoidType() diff --git a/example/expression/get_read_write.py b/example/expression/get_read_write.py index cf333d0c..752c4272 100644 --- a/example/expression/get_read_write.py +++ b/example/expression/get_read_write.py @@ -4,7 +4,7 @@ from future.utils import viewitems from miasm.arch.x86.arch import mn_x86 from miasm.expression.expression import get_rw -from miasm.arch.x86.ira import ir_a_x86_32 +from miasm.arch.x86.lifter_model_call import LifterModelCall_x86_32 from miasm.core.locationdb import LocationDB loc_db = LocationDB() @@ -16,7 +16,7 @@ Get read/written registers for a given instruction """) arch = mn_x86 -ir_arch = ir_a_x86_32(loc_db) +ir_arch = LifterModelCall_x86_32(loc_db) ircfg = ir_arch.new_ircfg() instr = arch.fromstring('LODSB', loc_db, 32) instr.offset, instr.l = 0, 15 diff --git a/example/expression/graph_dataflow.py b/example/expression/graph_dataflow.py index 4b428df7..661d0037 100644 --- a/example/expression/graph_dataflow.py +++ b/example/expression/graph_dataflow.py @@ -139,7 +139,7 @@ print('ok') print('generating dataflow graph for:') -ir_arch_analysis = machine.ira(loc_db) +ir_arch_analysis = machine.lifter_model_call(loc_db) ircfg = ir_arch_analysis.new_ircfg_from_asmcfg(asmcfg) deadrm = DeadRemoval(ir_arch_analysis) diff --git a/example/expression/solve_condition_stp.py b/example/expression/solve_condition_stp.py index 3743bfad..634e2337 100644 --- a/example/expression/solve_condition_stp.py +++ b/example/expression/solve_condition_stp.py @@ -30,7 +30,7 @@ if not args: sys.exit(0) -def emul_symb(ir_arch, ircfg, mdis, states_todo, states_done): +def emul_symb(lifter, ircfg, mdis, states_todo, states_done): while states_todo: addr, symbols, conds = states_todo.pop() print('*' * 40, "addr", addr, '*' * 40) @@ -38,11 +38,11 @@ def emul_symb(ir_arch, ircfg, mdis, states_todo, states_done): print('Known state, skipping', addr) continue states_done.add((addr, symbols, conds)) - symbexec = SymbolicExecutionEngine(ir_arch) + symbexec = SymbolicExecutionEngine(lifter) symbexec.symbols = symbols.copy() - if ir_arch.pc in symbexec.symbols: - del symbexec.symbols[ir_arch.pc] - irblock = get_block(ir_arch, ircfg, mdis, addr) + if lifter.pc in symbexec.symbols: + del symbexec.symbols[lifter.pc] + irblock = get_block(lifter, ircfg, mdis, addr) print('Run block:') print(irblock) @@ -87,9 +87,9 @@ if __name__ == '__main__': cont = Container.from_stream(open(args[0], 'rb'), loc_db) mdis = machine.dis_engine(cont.bin_stream, loc_db=loc_db) - ir_arch = machine.ir(mdis.loc_db) - ircfg = ir_arch.new_ircfg() - symbexec = SymbolicExecutionEngine(ir_arch) + lifter = machine.lifter(mdis.loc_db) + ircfg = lifter.new_ircfg() + symbexec = SymbolicExecutionEngine(lifter) asmcfg = parse_asm.parse_txt( machine.mn, 32, ''' @@ -129,19 +129,19 @@ if __name__ == '__main__': print(block) # add fake address and len to parsed instructions - ir_arch.add_asmblock_to_ircfg(block, ircfg) + lifter.add_asmblock_to_ircfg(block, ircfg) irb = ircfg.blocks[init_lbl] symbexec.eval_updt_irblock(irb) symbexec.dump(ids=False) - # reset ir_arch blocks - ir_arch.blocks = {} + # reset lifter blocks + lifter.blocks = {} states_todo = set() states_done = set() states_todo.add((addr, symbexec.symbols, ())) # emul blocks, propagate states - emul_symb(ir_arch, ircfg, mdis, states_todo, states_done) + emul_symb(lifter, ircfg, mdis, states_todo, states_done) all_info = [] @@ -156,7 +156,7 @@ if __name__ == '__main__': all_cases = set() - symbexec = SymbolicExecutionEngine(ir_arch) + symbexec = SymbolicExecutionEngine(lifter) for addr, reqs_cond in all_info: out = ['(set-logic QF_ABV)', '(set-info :smt-lib-version 2.0)'] diff --git a/example/ida/ctype_propagation.py b/example/ida/ctype_propagation.py index 1f55a975..3de81d0d 100644 --- a/example/ida/ctype_propagation.py +++ b/example/ida/ctype_propagation.py @@ -222,9 +222,9 @@ class CTypeEngineFixer(SymbExecCTypeFix): cst_propag_link) -def get_ira_call_fixer(ira): +def get_lifter_model_call_call_fixer(lifter_model_call): - class iraCallStackFixer(ira): + class lifter_model_callCallStackFixer(lifter_model_call): def call_effects(self, ad, instr): print(hex(instr.offset), instr) @@ -241,7 +241,7 @@ def get_ira_call_fixer(ira): ) return [call_assignblk], [] - return iraCallStackFixer + return lifter_model_callCallStackFixer def analyse_function(): @@ -262,7 +262,7 @@ def analyse_function(): # Init machine = guess_machine(addr=addr) - mn, dis_engine, ira = machine.mn, machine.dis_engine, machine.ira + mn, dis_engine, lifter_model_call = machine.mn, machine.dis_engine, machine.lifter_model_call bs = bin_stream_ida() loc_db = LocationDB() @@ -272,8 +272,8 @@ def analyse_function(): mdis.dont_dis = [end] - iraCallStackFixer = get_ira_call_fixer(ira) - ir_arch = iraCallStackFixer(loc_db) + lifter_model_callCallStackFixer = get_lifter_model_call_call_fixer(lifter_model_call) + ir_arch = lifter_model_callCallStackFixer(loc_db) asmcfg = mdis.dis_multiblock(addr) # Generate IR diff --git a/example/ida/depgraph.py b/example/ida/depgraph.py index e98d64c5..4a0fb1e9 100644 --- a/example/ida/depgraph.py +++ b/example/ida/depgraph.py @@ -26,9 +26,9 @@ from utils import guess_machine class depGraphSettingsForm(ida_kernwin.Form): - def __init__(self, ira, ircfg, mn): + def __init__(self, lifter_model_call, ircfg, mn): - self.ira = ira + self.lifter_model_call = lifter_model_call self.ircfg = ircfg self.mn = mn self.stk_args = {'ARG%d' % i:i for i in range(10)} @@ -51,7 +51,7 @@ class depGraphSettingsForm(ida_kernwin.Form): assert line_nb is not None cur_loc_key = str(cur_block.loc_key) loc_keys = sorted(map(str, ircfg.blocks)) - regs = sorted(ira.arch.regs.all_regs_ids_byname) + regs = sorted(lifter_model_call.arch.regs.all_regs_ids_byname) regs += list(self.stk_args) reg_default = regs[0] for i in range(10): @@ -130,13 +130,13 @@ Method to use: line = self.ircfg.blocks[self.loc_key][self.line_nb].instr arg_num = self.stk_args[value] stk_high = m2_expr.ExprInt(idc.get_spd(line.offset), ir_arch.sp.size) - stk_off = m2_expr.ExprInt(self.ira.sp.size // 8 * arg_num, ir_arch.sp.size) - element = m2_expr.ExprMem(self.mn.regs.regs_init[ir_arch.sp] + stk_high + stk_off, self.ira.sp.size) + stk_off = m2_expr.ExprInt(self.lifter_model_call.sp.size // 8 * arg_num, ir_arch.sp.size) + element = m2_expr.ExprMem(self.mn.regs.regs_init[ir_arch.sp] + stk_high + stk_off, self.lifter_model_call.sp.size) element = expr_simp(element) # Force stack unaliasing self.stk_unalias_force = True elif value: - element = self.ira.arch.regs.all_regs_ids_byname.get(value, None) + element = self.lifter_model_call.arch.regs.all_regs_ids_byname.get(value, None) else: raise ValueError("Unknown element '%s'!" % value) @@ -214,13 +214,13 @@ def launch_depgraph(): # Init machine = guess_machine(addr=func.start_ea) - mn, dis_engine, ira = machine.mn, machine.dis_engine, machine.ira + mn, dis_engine, lifter_model_call = machine.mn, machine.dis_engine, machine.lifter_model_call bs = bin_stream_ida() loc_db = LocationDB() mdis = dis_engine(bs, loc_db=loc_db, dont_dis_nulstart_bloc=True) - ir_arch = ira(loc_db) + ir_arch = lifter_model_call(loc_db) # Populate symbols with ida names for ad, name in idautils.Names(): diff --git a/example/ida/graph_ir.py b/example/ida/graph_ir.py index d10e1ebd..c827bbe2 100644 --- a/example/ida/graph_ir.py +++ b/example/ida/graph_ir.py @@ -180,9 +180,9 @@ def is_addr_ro_variable(bs, addr, size): def build_graph(start_addr, type_graph, simplify=False, use_ida_stack=True, dontmodstack=False, loadint=False, verbose=False): machine = guess_machine(addr=start_addr) - dis_engine, ira = machine.dis_engine, machine.ira + dis_engine, lifter_model_call = machine.dis_engine, machine.lifter_model_call - class IRADelModCallStack(ira): + class IRADelModCallStack(lifter_model_call): def call_effects(self, addr, instr): assignblks, extra = super(IRADelModCallStack, self).call_effects(addr, instr) if use_ida_stack: @@ -281,7 +281,7 @@ def build_graph(start_addr, type_graph, simplify=False, use_ida_stack=True, dont return - class IRAOutRegs(ira): + class IRAOutRegs(lifter_model_call): def get_out_regs(self, block): regs_todo = super(IRAOutRegs, self).get_out_regs(block) out = {} diff --git a/example/ida/symbol_exec.py b/example/ida/symbol_exec.py index b51ef9ee..ef5db082 100644 --- a/example/ida/symbol_exec.py +++ b/example/ida/symbol_exec.py @@ -150,11 +150,11 @@ def symbolic_exec(): mdis.dont_dis = [end] asmcfg = mdis.dis_multiblock(start) - ira = machine.ira(loc_db=loc_db) - ircfg = ira.new_ircfg_from_asmcfg(asmcfg) + lifter_model_call = machine.lifter_model_call(loc_db=loc_db) + ircfg = lifter_model_call.new_ircfg_from_asmcfg(asmcfg) print("Run symbolic execution...") - sb = SymbolicExecutionEngine(ira, machine.mn.regs.regs_init) + sb = SymbolicExecutionEngine(lifter_model_call, machine.mn.regs.regs_init) sb.run_at(ircfg, start) modified = {} diff --git a/example/symbol_exec/depgraph.py b/example/symbol_exec/depgraph.py index 8285452e..62190e6b 100644 --- a/example/symbol_exec/depgraph.py +++ b/example/symbol_exec/depgraph.py @@ -52,7 +52,7 @@ for element in args.element: raise ValueError("Unknown element '%s'" % element) mdis = machine.dis_engine(cont.bin_stream, dont_dis_nulstart_bloc=True, loc_db=loc_db) -ir_arch = machine.ira(loc_db) +ir_arch = machine.lifter_model_call(loc_db) # Common argument forms init_ctx = {} diff --git a/example/symbol_exec/dse_crackme.py b/example/symbol_exec/dse_crackme.py index e014ada2..cdaf5a1a 100644 --- a/example/symbol_exec/dse_crackme.py +++ b/example/symbol_exec/dse_crackme.py @@ -137,7 +137,7 @@ FILE_stream = ExprId("FILE_0", 64) FILE_size = ExprId("FILE_0_size", 64) def xxx_fopen_symb(dse): - regs = dse.ir_arch.arch.regs + regs = dse.lifter.arch.regs fname_addr = dse.eval_expr(regs.RDI) mode = dse.eval_expr(regs.RSI) assert fname_addr.is_int() @@ -151,13 +151,13 @@ def xxx_fopen_symb(dse): dse.update_state({ regs.RSP: dse.eval_expr(regs.RSP + ExprInt(8, regs.RSP.size)), - dse.ir_arch.IRDst: ret_addr, + dse.lifter.IRDst: ret_addr, regs.RIP: ret_addr, regs.RAX: ret_value, }) def xxx_fread_symb(dse): - regs = dse.ir_arch.arch.regs + regs = dse.lifter.arch.regs ptr = dse.eval_expr(regs.RDI) size = dse.eval_expr(regs.RSI) nmemb = dse.eval_expr(regs.RDX) @@ -179,21 +179,21 @@ def xxx_fread_symb(dse): update.update({ regs.RSP: dse.symb.eval_expr(regs.RSP + ExprInt(8, regs.RSP.size)), - dse.ir_arch.IRDst: ret_addr, + dse.lifter.IRDst: ret_addr, regs.RIP: ret_addr, regs.RAX: ret_value, }) dse.update_state(update) def xxx_fclose_symb(dse): - regs = dse.ir_arch.arch.regs + regs = dse.lifter.arch.regs stream = dse.eval_expr(regs.RDI) FILE_to_info_symb[stream].close() ret_addr = ExprInt(dse.jitter.get_stack_arg(0), regs.RIP.size) dse.update_state({ regs.RSP: dse.symb.eval_expr(regs.RSP + ExprInt(8, regs.RSP.size)), - dse.ir_arch.IRDst: ret_addr, + dse.lifter.IRDst: ret_addr, regs.RIP: ret_addr, regs.RAX: ExprInt(0, regs.RAX.size), }) @@ -203,7 +203,7 @@ def xxx_fclose_symb(dse): def xxx___libc_start_main_symb(dse): # ['RDI', 'RSI', 'RDX', 'RCX', 'R8', 'R9'] # main, argc, argv, ... - regs = dse.ir_arch.arch.regs + regs = dse.lifter.arch.regs top_stack = dse.eval_expr(regs.RSP) main_addr = dse.eval_expr(regs.RDI) argc = dse.eval_expr(regs.RSI) @@ -214,8 +214,8 @@ def xxx___libc_start_main_symb(dse): ExprMem(top_stack, 64): hlt_addr, regs.RDI: argc, regs.RSI: argv, - dse.ir_arch.IRDst: main_addr, - dse.ir_arch.pc: main_addr, + dse.lifter.IRDst: main_addr, + dse.lifter.pc: main_addr, }) # Stop the execution on puts and get back the corresponding string @@ -248,9 +248,9 @@ dse.attach(sb.jitter) # Update the jitter state: df is read, but never set # Approaches: specific or generic # - Specific: -# df_value = ExprInt(sb.jitter.cpu.df, dse.ir_arch.arch.regs.df.size) +# df_value = ExprInt(sb.jitter.cpu.df, dse.lifter.arch.regs.df.size) # dse.update_state({ -# dse.ir_arch.arch.regs.df: df_value +# dse.lifter.arch.regs.df: df_value # }) # - Generic: dse.update_state_from_concrete() diff --git a/example/symbol_exec/single_instr.py b/example/symbol_exec/single_instr.py index 789252df..0aabbf8b 100644 --- a/example/symbol_exec/single_instr.py +++ b/example/symbol_exec/single_instr.py @@ -21,12 +21,12 @@ mdis.lines_wd = 1 asm_block = mdis.dis_block(START_ADDR) # Translate ASM -> IR -ira = machine.ira(mdis.loc_db) -ircfg = ira.new_ircfg() -ira.add_asmblock_to_ircfg(asm_block, ircfg) +lifter_model_call = machine.lifter_model_call(mdis.loc_db) +ircfg = lifter_model_call.new_ircfg() +lifter_model_call.add_asmblock_to_ircfg(asm_block, ircfg) # Instantiate a Symbolic Execution engine with default value for registers -symb = SymbolicExecutionEngine(ira) +symb = SymbolicExecutionEngine(lifter_model_call) # Emulate one IR basic block ## Emulation of several basic blocks can be done through .emul_ir_blocks @@ -39,6 +39,6 @@ print('Modified memory (should be empty):') symb.dump(ids=False) # Check final status -eax, ebx = ira.arch.regs.EAX, ira.arch.regs.EBX +eax, ebx = lifter_model_call.arch.regs.EAX, lifter_model_call.arch.regs.EBX assert symb.symbols[eax] == ebx assert eax in symb.symbols diff --git a/miasm/analysis/cst_propag.py b/miasm/analysis/cst_propag.py index ba9b3aee..dd7733b0 100644 --- a/miasm/analysis/cst_propag.py +++ b/miasm/analysis/cst_propag.py @@ -122,7 +122,7 @@ def compute_cst_propagation_states(ir_arch, ircfg, init_addr, init_infos): The attribute "constant expression" is true if the expression is based on constants or "init" regs values. - @ir_arch: IntermediateRepresentation instance + @ir_arch: Lifter instance @init_addr: analysis start address @init_infos: dictionary linking expressions to their values at @init_addr """ @@ -169,7 +169,7 @@ def propagate_cst_expr(ir_arch, ircfg, addr, init_infos): The attribute "constant expression" is true if the expression is based on constants or "init" regs values. - @ir_arch: IntermediateRepresentation instance + @ir_arch: Lifter instance @addr: analysis start address @init_infos: dictionary linking expressions to their values at @init_addr diff --git a/miasm/analysis/data_flow.py b/miasm/analysis/data_flow.py index db8326ab..6ace4f4e 100644 --- a/miasm/analysis/data_flow.py +++ b/miasm/analysis/data_flow.py @@ -370,7 +370,7 @@ class DeadRemoval(object): Source : Kennedy, K. (1979). A survey of data flow analysis techniques. IBM Thomas J. Watson Research Division, page 43 - @ircfg: IntermediateRepresentation instance + @ircfg: Lifter instance """ modified = False @@ -793,7 +793,7 @@ def get_interval_length(interval_in): def check_expr_below_stack(ir_arch_a, expr): """ Return False if expr pointer is below original stack pointer - @ir_arch_a: ira instance + @ir_arch_a: lifter_model_call instance @expr: Expression instance """ ptr = expr.ptr @@ -809,7 +809,7 @@ def retrieve_stack_accesses(ir_arch_a, ircfg): """ Walk the ssa graph and find stack based variables. Return a dictionary linking stack base address to its size/name - @ir_arch_a: ira instance + @ir_arch_a: lifter_model_call instance @ircfg: IRCFG instance """ stack_vars = set() @@ -889,7 +889,7 @@ def replace_stack_vars(ir_arch_a, ircfg): WARNING: may fail - @ir_arch_a: ira instance + @ir_arch_a: lifter_model_call instance @ircfg: IRCFG instance """ @@ -949,7 +949,7 @@ def read_mem(bs, expr): def load_from_int(ir_arch, bs, is_addr_ro_variable): """ Replace memory read based on constant with static value - @ir_arch: ira instance + @ir_arch: lifter_model_call instance @bs: binstream instance @is_addr_ro_variable: callback(addr, size) to test memory candidate """ diff --git a/miasm/analysis/depgraph.py b/miasm/analysis/depgraph.py index ae853756..8b5c87e2 100644 --- a/miasm/analysis/depgraph.py +++ b/miasm/analysis/depgraph.py @@ -285,7 +285,7 @@ class DependencyResult(DependencyState): def emul(self, ir_arch, ctx=None, step=False): """Symbolic execution of relevant nodes according to the history Return the values of inputs nodes' elements - @ir_arch: IntermediateRepresentation instance + @ir_arch: Lifter instance @ctx: (optional) Initial context as dictionary @step: (optional) Verbose execution Warning: The emulation is not sound if the inputs nodes depend on loop diff --git a/miasm/analysis/disasm_cb.py b/miasm/analysis/disasm_cb.py index af47603b..a3d7a68c 100644 --- a/miasm/analysis/disasm_cb.py +++ b/miasm/analysis/disasm_cb.py @@ -11,26 +11,26 @@ from miasm.core.locationdb import LocationDB from miasm.core.utils import upck32 -def get_ira(arch, attrib): +def get_lifter_model_call(arch, attrib): arch = arch.name, attrib if arch == ("arm", "arm"): - from miasm.arch.arm.ira import ir_a_arm_base as ira + from miasm.arch.arm.lifter_model_call import LifterModelCallArmlBase as lifter_model_call elif arch == ("x86", 32): - from miasm.arch.x86.ira import ir_a_x86_32 as ira + from miasm.arch.x86.lifter_model_call import LifterModelCall_x86_32 as lifter_model_call elif arch == ("x86", 64): - from miasm.arch.x86.ira import ir_a_x86_64 as ira + from miasm.arch.x86.lifter_model_call import LifterModelCall_x86_64 as lifter_model_call else: raise ValueError('unknown architecture: %s' % arch.name) - return ira + return lifter_model_call def arm_guess_subcall(dis_engine, cur_block, offsets_to_dis): arch = dis_engine.arch loc_db = dis_engine.loc_db - ira = get_ira(arch, dis_engine.attrib) + lifter_model_call = get_lifter_model_call(arch, dis_engine.attrib) - ir_arch = ira(loc_db) - ircfg = ira.new_ircfg() + ir_arch = lifter_model_call(loc_db) + ircfg = lifter_model_call.new_ircfg() print('###') print(cur_block) ir_arch.add_asmblock_to_ircfg(cur_block, ircfg) @@ -66,13 +66,13 @@ def arm_guess_subcall(dis_engine, cur_block, offsets_to_dis): def arm_guess_jump_table(dis_engine, cur_block, offsets_to_dis): arch = dis_engine.arch loc_db = dis_engine.loc_db - ira = get_ira(arch, dis_engine.attrib) + lifter_model_call = get_lifter_model_call(arch, dis_engine.attrib) jra = ExprId('jra') jrb = ExprId('jrb') - ir_arch = ira(loc_db) - ircfg = ira.new_ircfg() + ir_arch = lifter_model_call(loc_db) + ircfg = lifter_model_call.new_ircfg() ir_arch.add_asmblock_to_ircfg(cur_block, ircfg) for irblock in viewvalues(ircfg.blocks): diff --git a/miasm/analysis/dse.py b/miasm/analysis/dse.py index cfd13821..5e6c4e8d 100644 --- a/miasm/analysis/dse.py +++ b/miasm/analysis/dse.py @@ -49,6 +49,7 @@ Here are a few remainings TODO: """ from builtins import range from collections import namedtuple +import warnings try: import z3 @@ -167,8 +168,8 @@ class DSEEngine(object): self.handler = {} # addr -> callback(DSEEngine instance) self.instrumentation = {} # addr -> callback(DSEEngine instance) self.addr_to_cacheblocks = {} # addr -> {label -> IRBlock} - self.ir_arch = self.machine.ir(loc_db=self.loc_db) # corresponding IR - self.ircfg = self.ir_arch.new_ircfg() # corresponding IR + self.lifter = self.machine.lifter(loc_db=self.loc_db) # corresponding IR + self.ircfg = self.lifter.new_ircfg() # corresponding IR # Defined after attachment self.jitter = None # Jitload (concrete execution) @@ -186,17 +187,17 @@ class DSEEngine(object): # Symbexec engine ## Prepare symbexec engines self.symb = self.SYMB_ENGINE(self.jitter.cpu, self.jitter.vm, - self.ir_arch, {}) + self.lifter, {}) self.symb.enable_emulated_simplifications() self.symb_concrete = ESENoVMSideEffects( self.jitter.cpu, self.jitter.vm, - self.ir_arch, {} + self.lifter, {} ) ## Update registers value - self.symb.symbols[self.ir_arch.IRDst] = ExprInt( - getattr(self.jitter.cpu, self.ir_arch.pc.name), - self.ir_arch.IRDst.size + self.symb.symbols[self.lifter.IRDst] = ExprInt( + getattr(self.jitter.cpu, self.lifter.pc.name), + self.lifter.IRDst.size ) # Activate callback on each instr @@ -288,7 +289,7 @@ class DSEEngine(object): for symbol in self.symb.modified_expr: # Do not consider PC - if symbol in [self.ir_arch.pc, self.ir_arch.IRDst]: + if symbol in [self.lifter.pc, self.lifter.IRDst]: continue # Consider only concrete values @@ -324,7 +325,7 @@ class DSEEngine(object): # Call callbacks associated to the current address cur_addr = self.jitter.pc if isinstance(cur_addr, LocKey): - lbl = self.ir_arch.loc_db.loc_key_to_label(cur_addr) + lbl = self.lifter.loc_db.loc_key_to_label(cur_addr) cur_addr = lbl.offset if cur_addr in self.handler: @@ -335,7 +336,7 @@ class DSEEngine(object): self.instrumentation[cur_addr](self) # Handle current address - self.handle(ExprInt(cur_addr, self.ir_arch.IRDst.size)) + self.handle(ExprInt(cur_addr, self.lifter.IRDst.size)) # Avoid memory issue in ExpressionSimplifier if len(self.symb.expr_simp.cache) > 100000: @@ -352,7 +353,7 @@ class DSEEngine(object): ## Update current state asm_block = self.mdis.dis_block(cur_addr) - self.ir_arch.add_asmblock_to_ircfg(asm_block, self.ircfg) + self.lifter.add_asmblock_to_ircfg(asm_block, self.ircfg) self.addr_to_cacheblocks[cur_addr] = dict(self.ircfg.blocks) # Emulate the current instruction @@ -379,7 +380,7 @@ class DSEEngine(object): self.symb.run_block_at(self.ircfg, cur_addr) if not (isinstance(next_addr_concrete, ExprLoc) and - self.ir_arch.loc_db.get_location_offset( + self.lifter.loc_db.get_location_offset( next_addr_concrete.loc_key ) is None): # Not a lbl_gen, exit @@ -400,7 +401,7 @@ class DSEEngine(object): This version use the regs associated to the attrib (!= cpu.get_gpreg()) """ out = {} - regs = self.ir_arch.arch.regs.attrib_to_regs[self.ir_arch.attrib] + regs = self.lifter.arch.regs.attrib_to_regs[self.lifter.attrib] for reg in regs: if hasattr(self.jitter.cpu, reg.name): out[reg.name] = getattr(self.jitter.cpu, reg.name) @@ -432,7 +433,7 @@ class DSEEngine(object): ) # Restore registers - self.jitter.pc = snapshot["regs"][self.ir_arch.pc.name] + self.jitter.pc = snapshot["regs"][self.lifter.pc.name] for reg, value in viewitems(snapshot["regs"]): setattr(self.jitter.cpu, reg, value) @@ -460,7 +461,7 @@ class DSEEngine(object): # not present symbexec.symbols.symbols_mem.base_to_memarray.clear() if cpu: - regs = self.ir_arch.arch.regs.attrib_to_regs[self.ir_arch.attrib] + regs = self.lifter.arch.regs.attrib_to_regs[self.lifter.attrib] for reg in regs: if hasattr(self.jitter.cpu, reg.name): value = ExprInt(getattr(self.jitter.cpu, reg.name), @@ -548,6 +549,11 @@ class DSEPathConstraint(DSEEngine): if produce_solution == self.PRODUCE_SOLUTION_PATH_COV: self._history = [] # List of addresses in the current path + @property + def ir_arch(self): + warnings.warn('DEPRECATION WARNING: use ".lifter" instead of ".ir_arch"') + return self.lifter + def take_snapshot(self, *args, **kwargs): snap = super(DSEPathConstraint, self).take_snapshot(*args, **kwargs) snap["new_solutions"] = { @@ -638,17 +644,17 @@ class DSEPathConstraint(DSEEngine): self.cur_solver.add(self.z3_trans.from_expr(cons)) def handle(self, cur_addr): - cur_addr = canonize_to_exprloc(self.ir_arch.loc_db, cur_addr) - symb_pc = self.eval_expr(self.ir_arch.IRDst) + cur_addr = canonize_to_exprloc(self.lifter.loc_db, cur_addr) + symb_pc = self.eval_expr(self.lifter.IRDst) possibilities = possible_values(symb_pc) cur_path_constraint = set() # path_constraint for the concrete path if len(possibilities) == 1: dst = next(iter(possibilities)).value - dst = canonize_to_exprloc(self.ir_arch.loc_db, dst) + dst = canonize_to_exprloc(self.lifter.loc_db, dst) assert dst == cur_addr else: for possibility in possibilities: - target_addr = canonize_to_exprloc(self.ir_arch.loc_db, possibility.value) + target_addr = canonize_to_exprloc(self.lifter.loc_db, possibility.value) path_constraint = set() # Set of ExprAssign for the possible path # Get constraint associated to the possible path @@ -682,7 +688,7 @@ class DSEPathConstraint(DSEEngine): for start, stop in memory_to_add: for address in range(start, stop + 1): expr_mem = ExprMem(ExprInt(address, - self.ir_arch.pc.size), + self.lifter.pc.size), 8) value = self.eval_expr(expr_mem) if not value.is_int(): diff --git a/miasm/analysis/machine.py b/miasm/analysis/machine.py index ba076d8c..bf3cc6f8 100644 --- a/miasm/analysis/machine.py +++ b/miasm/analysis/machine.py @@ -1,4 +1,5 @@ #-*- coding:utf-8 -*- +import warnings class Machine(object): @@ -6,7 +7,7 @@ class Machine(object): __dis_engine = None # Disassembly engine __mn = None # Machine instance - __ira = None # IR analyser + __lifter_model_call = None # IR analyser __jitter = None # Jit engine __gdbserver = None # GdbServer handler @@ -19,7 +20,7 @@ class Machine(object): dis_engine = None mn = None - ira = None + lifter_model_call = None ir = None jitter = None gdbserver = None @@ -38,8 +39,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_arm - from miasm.arch.arm.ira import ir_a_arml as ira - from miasm.arch.arm.sem import ir_arml as ir + from miasm.arch.arm.lifter_model_call import LifterModelCallArml as lifter_model_call + from miasm.arch.arm.sem import Lifter_Arml as lifter elif machine_name == "armb": from miasm.arch.arm.disasm import dis_armb as dis_engine from miasm.arch.arm import arch @@ -49,8 +50,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_arm - from miasm.arch.arm.ira import ir_a_armb as ira - from miasm.arch.arm.sem import ir_armb as ir + from miasm.arch.arm.lifter_model_call import LifterModelCallArmb as lifter_model_call + from miasm.arch.arm.sem import Lifter_Armb as lifter elif machine_name == "aarch64l": from miasm.arch.aarch64.disasm import dis_aarch64l as dis_engine from miasm.arch.aarch64 import arch @@ -60,8 +61,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_aarch64 - from miasm.arch.aarch64.ira import ir_a_aarch64l as ira - from miasm.arch.aarch64.sem import ir_aarch64l as ir + from miasm.arch.aarch64.lifter_model_call import LifterModelCallAarch64l as lifter_model_call + from miasm.arch.aarch64.sem import Lifter_Aarch64l as lifter elif machine_name == "aarch64b": from miasm.arch.aarch64.disasm import dis_aarch64b as dis_engine from miasm.arch.aarch64 import arch @@ -71,14 +72,14 @@ class Machine(object): except ImportError: pass mn = arch.mn_aarch64 - from miasm.arch.aarch64.ira import ir_a_aarch64b as ira - from miasm.arch.aarch64.sem import ir_aarch64b as ir + from miasm.arch.aarch64.lifter_model_call import LifterModelCallAarch64b as lifter_model_call + from miasm.arch.aarch64.sem import Lifter_Aarch64b as lifter elif machine_name == "armtl": from miasm.arch.arm.disasm import dis_armtl as dis_engine from miasm.arch.arm import arch mn = arch.mn_armt - from miasm.arch.arm.ira import ir_a_armtl as ira - from miasm.arch.arm.sem import ir_armtl as ir + from miasm.arch.arm.lifter_model_call import LifterModelCallArmtl as lifter_model_call + from miasm.arch.arm.sem import Lifter_Armtl as lifter try: from miasm.arch.arm import jit jitter = jit.jitter_armtl @@ -88,8 +89,8 @@ class Machine(object): from miasm.arch.arm.disasm import dis_armtb as dis_engine from miasm.arch.arm import arch mn = arch.mn_armt - from miasm.arch.arm.ira import ir_a_armtb as ira - from miasm.arch.arm.sem import ir_armtb as ir + from miasm.arch.arm.lifter_model_call import LifterModelCallArmtb as lifter_model_call + from miasm.arch.arm.sem import Lifter_Armtb as lifter elif machine_name == "sh4": from miasm.arch.sh4 import arch mn = arch.mn_sh4 @@ -102,8 +103,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_x86 - from miasm.arch.x86.ira import ir_a_x86_16 as ira - from miasm.arch.x86.sem import ir_x86_16 as ir + from miasm.arch.x86.lifter_model_call import LifterModelCall_x86_16 as lifter_model_call + from miasm.arch.x86.sem import Lifter_X86_16 as lifter elif machine_name == "x86_32": from miasm.arch.x86.disasm import dis_x86_32 as dis_engine from miasm.arch.x86 import arch @@ -113,8 +114,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_x86 - from miasm.arch.x86.ira import ir_a_x86_32 as ira - from miasm.arch.x86.sem import ir_x86_32 as ir + from miasm.arch.x86.lifter_model_call import LifterModelCall_x86_32 as lifter_model_call + from miasm.arch.x86.sem import Lifter_X86_32 as lifter try: from miasm.analysis.gdbserver import GdbServer_x86_32 as gdbserver except ImportError: @@ -128,8 +129,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_x86 - from miasm.arch.x86.ira import ir_a_x86_64 as ira - from miasm.arch.x86.sem import ir_x86_64 as ir + from miasm.arch.x86.lifter_model_call import LifterModelCall_x86_64 as lifter_model_call + from miasm.arch.x86.sem import Lifter_X86_64 as lifter elif machine_name == "msp430": from miasm.arch.msp430.disasm import dis_msp430 as dis_engine from miasm.arch.msp430 import arch @@ -139,8 +140,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_msp430 - from miasm.arch.msp430.ira import ir_a_msp430 as ira - from miasm.arch.msp430.sem import ir_msp430 as ir + from miasm.arch.msp430.lifter_model_call import LifterModelCallMsp430 as lifter_model_call + from miasm.arch.msp430.sem import Lifter_MSP430 as lifter try: from miasm.analysis.gdbserver import GdbServer_msp430 as gdbserver except ImportError: @@ -154,8 +155,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_mips32 - from miasm.arch.mips32.ira import ir_a_mips32b as ira - from miasm.arch.mips32.sem import ir_mips32b as ir + from miasm.arch.mips32.lifter_model_call import LifterModelCallMips32b as lifter_model_call + from miasm.arch.mips32.sem import Lifter_Mips32b as lifter elif machine_name == "mips32l": from miasm.arch.mips32.disasm import dis_mips32l as dis_engine from miasm.arch.mips32 import arch @@ -165,8 +166,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_mips32 - from miasm.arch.mips32.ira import ir_a_mips32l as ira - from miasm.arch.mips32.sem import ir_mips32l as ir + from miasm.arch.mips32.lifter_model_call import LifterModelCallMips32l as lifter_model_call + from miasm.arch.mips32.sem import Lifter_Mips32l as lifter elif machine_name == "ppc32b": from miasm.arch.ppc.disasm import dis_ppc32b as dis_engine from miasm.arch.ppc import arch @@ -176,8 +177,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_ppc - from miasm.arch.ppc.ira import ir_a_ppc32b as ira - from miasm.arch.ppc.sem import ir_ppc32b as ir + from miasm.arch.ppc.lifter_model_call import LifterModelCallPpc32b as lifter_model_call + from miasm.arch.ppc.sem import Lifter_PPC32b as lifter elif machine_name == "mepb": from miasm.arch.mep.disasm import dis_mepb as dis_engine from miasm.arch.mep import arch @@ -187,8 +188,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_mep - from miasm.arch.mep.ira import ir_a_mepb as ira - from miasm.arch.mep.sem import ir_mepb as ir + from miasm.arch.mep.lifter_model_call import LifterModelCallMepb as lifter_model_call + from miasm.arch.mep.sem import Lifter_MEPb as lifter elif machine_name == "mepl": from miasm.arch.mep.disasm import dis_mepl as dis_engine from miasm.arch.mep import arch @@ -198,8 +199,8 @@ class Machine(object): except ImportError: pass mn = arch.mn_mep - from miasm.arch.mep.ira import ir_a_mepl as ira - from miasm.arch.mep.sem import ir_mepl as ir + from miasm.arch.mep.lifter_model_call import LifterModelCallMepl as lifter_model_call + from miasm.arch.mep.sem import Lifter_MEPl as lifter else: raise ValueError('Unknown machine: %s' % machine_name) @@ -210,13 +211,13 @@ class Machine(object): self.__dis_engine = dis_engine self.__mn = mn - self.__ira = ira + self.__lifter_model_call = lifter_model_call self.__jitter = jitter self.__gdbserver = gdbserver self.__log_jit = log_jit self.__log_arch = log_arch self.__base_expr = arch.base_expr - self.__ir = ir + self.__lifter = lifter self.__name = machine_name @property @@ -228,8 +229,12 @@ class Machine(object): return self.__mn @property - def ira(self): - return self.__ira + def lifter(self): + return self.__lifter + + @property + def lifter_model_call(self): + return self.__lifter_model_call @property def ir(self): @@ -263,3 +268,13 @@ class Machine(object): def available_machine(cls): "Return a list of supported machines" return cls.__available + + @property + def ira(self): + warnings.warn('DEPRECATION WARNING: use ".lifter_model_call" instead of ".ira"') + return self.lifter_model_call + + @property + def ir(self): + warnings.warn('DEPRECATION WARNING: use ".lifter" instead of ".ir"') + return self.lifter diff --git a/miasm/analysis/simplifier.py b/miasm/analysis/simplifier.py index 51567e64..193b329c 100644 --- a/miasm/analysis/simplifier.py +++ b/miasm/analysis/simplifier.py @@ -3,6 +3,7 @@ Apply simplification passes to an IR cfg """ import logging +import warnings from functools import wraps from miasm.analysis.ssa import SSADiGraph from miasm.analysis.outofssa import UnSSADiGraph @@ -46,10 +47,16 @@ class IRCFGSimplifier(object): This class applies passes until reaching a fix point """ - def __init__(self, ir_arch): - self.ir_arch = ir_arch + def __init__(self, lifter): + self.lifter = lifter self.init_passes() + @property + def ir_arch(self): + fds + warnings.warn('DEPRECATION WARNING: use ".lifter" instead of ".ir_arch"') + return self.lifter + def init_passes(self): """ Init the array of simplification passes @@ -81,10 +88,10 @@ class IRCFGSimplifierCommon(IRCFGSimplifier): - simplify_ircfg - do_dead_simp_ircfg """ - def __init__(self, ir_arch, expr_simp=expr_simp): + def __init__(self, lifter, expr_simp=expr_simp): self.expr_simp = expr_simp - super(IRCFGSimplifierCommon, self).__init__(ir_arch) - self.deadremoval = DeadRemoval(self.ir_arch) + super(IRCFGSimplifierCommon, self).__init__(lifter) + self.deadremoval = DeadRemoval(self.lifter) def init_passes(self): self.passes = [ @@ -133,10 +140,10 @@ class IRCFGSimplifierSSA(IRCFGSimplifierCommon): - do_dead_simp_ssa """ - def __init__(self, ir_arch, expr_simp=expr_simp): - super(IRCFGSimplifierSSA, self).__init__(ir_arch, expr_simp) + def __init__(self, lifter, expr_simp=expr_simp): + super(IRCFGSimplifierSSA, self).__init__(lifter, expr_simp) - self.ir_arch.ssa_var = {} + self.lifter.ssa_var = {} self.all_ssa_vars = {} self.ssa_forbidden_regs = self.get_forbidden_regs() @@ -144,7 +151,7 @@ class IRCFGSimplifierSSA(IRCFGSimplifierCommon): self.propag_expressions = PropagateExpressions() self.del_dummy_phi = DelDummyPhi() - self.deadremoval = DeadRemoval(self.ir_arch, self.all_ssa_vars) + self.deadremoval = DeadRemoval(self.lifter, self.all_ssa_vars) def get_forbidden_regs(self): """ @@ -152,9 +159,9 @@ class IRCFGSimplifierSSA(IRCFGSimplifierCommon): """ regs = set( [ - self.ir_arch.pc, - self.ir_arch.IRDst, - self.ir_arch.arch.regs.exception_flags + self.lifter.pc, + self.lifter.IRDst, + self.lifter.arch.regs.exception_flags ] ) return regs @@ -187,7 +194,7 @@ class IRCFGSimplifierSSA(IRCFGSimplifierCommon): ssa.ssa_variable_to_expr.update(self.all_ssa_vars) ssa.transform(head) self.all_ssa_vars.update(ssa.ssa_variable_to_expr) - self.ir_arch.ssa_var.update(ssa.ssa_variable_to_expr) + self.lifter.ssa_var.update(ssa.ssa_variable_to_expr) return ssa def ssa_to_unssa(self, ssa, head): @@ -198,7 +205,7 @@ class IRCFGSimplifierSSA(IRCFGSimplifierCommon): @head: Location instance of the graph head """ cfg_liveness = DiGraphLivenessSSA(ssa.graph) - cfg_liveness.init_var_info(self.ir_arch) + cfg_liveness.init_var_info(self.lifter) cfg_liveness.compute_liveness() UnSSADiGraph(ssa, head, cfg_liveness) @@ -313,7 +320,7 @@ class IRCFGSimplifierSSA(IRCFGSimplifierCommon): ssa = self.ircfg_to_ssa(ircfg, head) ssa = self.do_simplify_loop(ssa, head) ircfg = self.ssa_to_unssa(ssa, head) - ircfg_simplifier = IRCFGSimplifierCommon(self.ir_arch) + ircfg_simplifier = IRCFGSimplifierCommon(self.lifter) ircfg_simplifier.deadremoval.add_expr_to_original_expr(self.all_ssa_vars) ircfg_simplifier.simplify(ircfg, head) return ircfg diff --git a/miasm/arch/aarch64/jit.py b/miasm/arch/aarch64/jit.py index 52ef1ae7..f71ecae4 100644 --- a/miasm/arch/aarch64/jit.py +++ b/miasm/arch/aarch64/jit.py @@ -3,7 +3,7 @@ import logging from miasm.jitter.jitload import Jitter, named_arguments from miasm.core.utils import pck64, upck64 -from miasm.arch.aarch64.sem import ir_aarch64b, ir_aarch64l +from miasm.arch.aarch64.sem import Lifter_Aarch64b, Lifter_Aarch64l log = logging.getLogger('jit_aarch64') hnd = logging.StreamHandler() @@ -15,7 +15,7 @@ class jitter_aarch64l(Jitter): max_reg_arg = 8 def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_aarch64l(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_Aarch64l(loc_db), *args, **kwargs) self.vm.set_little_endian() def push_uint64_t(self, value): @@ -75,5 +75,5 @@ class jitter_aarch64l(Jitter): class jitter_aarch64b(jitter_aarch64l): def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_aarch64b(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_Aarch64b(loc_db), *args, **kwargs) self.vm.set_big_endian() diff --git a/miasm/arch/aarch64/ira.py b/miasm/arch/aarch64/lifter_model_call.py index aded3dd1..74f25969 100644 --- a/miasm/arch/aarch64/ira.py +++ b/miasm/arch/aarch64/lifter_model_call.py @@ -1,27 +1,27 @@ #-*- coding:utf-8 -*- -from miasm.ir.analysis import ira -from miasm.arch.aarch64.sem import ir_aarch64l, ir_aarch64b +from miasm.ir.analysis import LifterModelCall +from miasm.arch.aarch64.sem import Lifter_Aarch64l, Lifter_Aarch64b -class ir_a_aarch64l_base(ir_aarch64l, ira): +class LifterModelCallAarch64lBase(Lifter_Aarch64l, LifterModelCall): def __init__(self, loc_db): - ir_aarch64l.__init__(self, loc_db) + Lifter_Aarch64l.__init__(self, loc_db) self.ret_reg = self.arch.regs.X0 -class ir_a_aarch64b_base(ir_aarch64b, ira): +class LifterModelCallAarch64bBase(Lifter_Aarch64b, LifterModelCall): def __init__(self, loc_db): - ir_aarch64b.__init__(self, loc_db) + Lifter_Aarch64b.__init__(self, loc_db) self.ret_reg = self.arch.regs.X0 -class ir_a_aarch64l(ir_a_aarch64l_base): +class LifterModelCallAarch64l(LifterModelCallAarch64lBase): def __init__(self, loc_db): - ir_a_aarch64l_base.__init__(self, loc_db) + LifterModelCallAarch64lBase.__init__(self, loc_db) self.ret_reg = self.arch.regs.X0 def get_out_regs(self, _): @@ -43,8 +43,8 @@ class ir_a_aarch64l(ir_a_aarch64l_base): return 32 -class ir_a_aarch64b(ir_a_aarch64b_base, ir_a_aarch64l): +class LifterModelCallAarch64b(LifterModelCallAarch64bBase, LifterModelCallAarch64l): def __init__(self, loc_db): - ir_a_aarch64b_base.__init__(self, loc_db) + LifterModelCallAarch64bBase.__init__(self, loc_db) self.ret_reg = self.arch.regs.X0 diff --git a/miasm/arch/aarch64/sem.py b/miasm/arch/aarch64/sem.py index 6629cf0d..8a084ea7 100644 --- a/miasm/arch/aarch64/sem.py +++ b/miasm/arch/aarch64/sem.py @@ -3,7 +3,7 @@ from future.utils import viewitems from miasm.expression.expression import ExprId, ExprInt, ExprLoc, ExprMem, \ ExprCond, ExprCompose, ExprOp, ExprAssign -from miasm.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock +from miasm.ir.ir import Lifter, IRBlock, AssignBlock from miasm.arch.aarch64.arch import mn_aarch64, conds_expr, replace_regs from miasm.arch.aarch64.regs import * from miasm.core.sembuilder import SemBuilder @@ -2285,10 +2285,10 @@ class aarch64info(object): # offset -class ir_aarch64l(IntermediateRepresentation): +class Lifter_Aarch64l(Lifter): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_aarch64, "l", loc_db) + Lifter.__init__(self, mn_aarch64, "l", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 64) @@ -2371,10 +2371,10 @@ class ir_aarch64l(IntermediateRepresentation): return instr_ir, new_irblocks -class ir_aarch64b(ir_aarch64l): +class Lifter_Aarch64b(Lifter_Aarch64l): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_aarch64, "b", loc_db) + Lifter.__init__(self, mn_aarch64, "b", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 64) diff --git a/miasm/arch/arm/jit.py b/miasm/arch/arm/jit.py index b4b7e793..78a69027 100644 --- a/miasm/arch/arm/jit.py +++ b/miasm/arch/arm/jit.py @@ -3,7 +3,7 @@ import logging from miasm.jitter.jitload import Jitter, named_arguments from miasm.core.utils import pck32, upck32 -from miasm.arch.arm.sem import ir_armb, ir_arml, ir_armtl, ir_armtb, cond_dct_inv, tab_cond +from miasm.arch.arm.sem import Lifter_Armb, Lifter_Arml, Lifter_Armtl, Lifter_Armtb, cond_dct_inv, tab_cond from miasm.jitter.codegen import CGen from miasm.expression.expression import ExprId, ExprAssign, ExprCond from miasm.ir.ir import IRBlock, AssignBlock @@ -65,7 +65,7 @@ class jitter_arml(Jitter): C_Gen = arm_CGen def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_arml(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_Arml(loc_db), *args, **kwargs) self.vm.set_little_endian() def push_uint32_t(self, value): @@ -132,7 +132,7 @@ class jitter_armb(jitter_arml): C_Gen = arm_CGen def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_armb(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_Armb(loc_db), *args, **kwargs) self.vm.set_big_endian() @@ -140,5 +140,5 @@ class jitter_armtl(jitter_arml): C_Gen = arm_CGen def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_armtl(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_Armtl(loc_db), *args, **kwargs) self.vm.set_little_endian() diff --git a/miasm/arch/arm/ira.py b/miasm/arch/arm/lifter_model_call.py index f2d8d44b..f9c39ab6 100644 --- a/miasm/arch/arm/ira.py +++ b/miasm/arch/arm/lifter_model_call.py @@ -1,26 +1,26 @@ #-*- coding:utf-8 -*- -from miasm.ir.analysis import ira +from miasm.ir.analysis import LifterModelCall from miasm.ir.ir import IRBlock -from miasm.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb, tab_cond +from miasm.arch.arm.sem import Lifter_Arml, Lifter_Armtl, Lifter_Armb, Lifter_Armtb, tab_cond from miasm.expression.expression import ExprAssign, ExprOp, ExprLoc, ExprCond from miasm.ir.ir import AssignBlock -class ir_a_arml_base(ir_arml, ira): +class LifterModelCallArmlBase(Lifter_Arml, LifterModelCall): def __init__(self, loc_db): - ir_arml.__init__(self, loc_db) + Lifter_Arml.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 -class ir_a_armb_base(ir_armb, ira): +class LifterModelCallArmbBase(Lifter_Armb, LifterModelCall): def __init__(self, loc_db): - ir_armb.__init__(self, loc_db) + Lifter_Armb.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 -class ir_a_arml(ir_a_arml_base): +class LifterModelCallArml(LifterModelCallArmlBase): def __init__(self, loc_db): - ir_a_arml_base.__init__(self, loc_db) + LifterModelCallArmlBase.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 def call_effects(self, ad, instr): @@ -88,19 +88,19 @@ class ir_a_arml(ir_a_arml_base): def sizeof_pointer(self): return 32 -class ir_a_armb(ir_a_armb_base, ir_a_arml): +class LifterModelCallArmb(LifterModelCallArmbBase, LifterModelCallArml): def __init__(self, loc_db): - ir_a_armb_base.__init__(self, loc_db) + LifterModelCallArmbBase.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 -class ir_a_armtl(ir_armtl, ir_a_arml): +class LifterModelCallArmtl(Lifter_Armtl, LifterModelCallArml): def __init__(self, loc_db): - ir_armtl.__init__(self, loc_db) + Lifter_Armtl.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 -class ir_a_armtb(ir_a_armtl, ir_armtb, ir_a_armb): +class LifterModelCallArmtb(LifterModelCallArmtl, Lifter_Armtb, LifterModelCallArmb): def __init__(self, loc_db): - ir_armtb.__init__(self, loc_db) + Lifter_Armtb.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 diff --git a/miasm/arch/arm/sem.py b/miasm/arch/arm/sem.py index fd82df23..e507a045 100644 --- a/miasm/arch/arm/sem.py +++ b/miasm/arch/arm/sem.py @@ -2,7 +2,7 @@ from builtins import range from future.utils import viewitems, viewvalues from miasm.expression.expression import * -from miasm.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock +from miasm.ir.ir import Lifter, IRBlock, AssignBlock from miasm.arch.arm.arch import mn_arm, mn_armt from miasm.arch.arm.regs import * @@ -1932,9 +1932,9 @@ class arminfo(object): # offset -class ir_arml(IntermediateRepresentation): +class Lifter_Arml(Lifter): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_arm, "l", loc_db) + Lifter.__init__(self, mn_arm, "l", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) @@ -2129,18 +2129,18 @@ class ir_arml(IntermediateRepresentation): -class ir_armb(ir_arml): +class Lifter_Armb(Lifter_Arml): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_arm, "b", loc_db) + Lifter.__init__(self, mn_arm, "b", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) self.addrsize = 32 -class ir_armtl(ir_arml): +class Lifter_Armtl(Lifter_Arml): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_armt, "l", loc_db) + Lifter.__init__(self, mn_armt, "l", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) @@ -2164,9 +2164,9 @@ class ir_armtl(ir_arml): lambda expr: expr.replace_expr(pc_fixed)) -class ir_armtb(ir_armtl): +class Lifter_Armtb(Lifter_Armtl): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_armt, "b", loc_db) + Lifter.__init__(self, mn_armt, "b", loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 32) diff --git a/miasm/arch/mep/jit.py b/miasm/arch/mep/jit.py index cc1e56ac..e3cd2428 100644 --- a/miasm/arch/mep/jit.py +++ b/miasm/arch/mep/jit.py @@ -6,7 +6,7 @@ from miasm.jitter.jitload import Jitter from miasm.core.utils import * from miasm.jitter.codegen import CGen from miasm.ir.translators.C import TranslatorC -from miasm.arch.mep.sem import ir_mepl, ir_mepb +from miasm.arch.mep.sem import Lifter_MEPl, Lifter_MEPb import logging @@ -77,7 +77,7 @@ class jitter_mepl(Jitter): C_Gen = mep_CGen def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_mepl(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_MEPl(loc_db), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC @@ -107,6 +107,6 @@ class jitter_mepl(Jitter): class jitter_mepb(jitter_mepl): def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_mepb(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_MEPb(loc_db), *args, **kwargs) self.vm.set_big_endian() self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC diff --git a/miasm/arch/mep/ira.py b/miasm/arch/mep/lifter_model_call.py index eac4f6e9..db729ba0 100644 --- a/miasm/arch/mep/ira.py +++ b/miasm/arch/mep/lifter_model_call.py @@ -1,11 +1,11 @@ # Toshiba MeP-c4 - miasm IR analysis # Guillaume Valadon <guillaume@valadon.net> -from miasm.arch.mep.sem import ir_mepb, ir_mepl -from miasm.ir.analysis import ira +from miasm.arch.mep.sem import Lifter_MEPb, Lifter_MEPl +from miasm.ir.analysis import LifterModelCall -class ir_a_mepb(ir_mepb, ira): +class LifterModelCallMepb(Lifter_MEPb, LifterModelCall): """MeP high level IR manipulations - Big Endian Notes: @@ -13,7 +13,7 @@ class ir_a_mepb(ir_mepb, ira): """ def __init__(self, loc_db): - ir_mepb.__init__(self, loc_db) + Lifter_MEPb.__init__(self, loc_db) self.ret_reg = self.arch.regs.R0 # Note: the following are abstract method and must be implemented @@ -38,8 +38,8 @@ class ir_a_mepb(ir_mepb, ira): return 32 -class ir_a_mepl(ir_mepl, ir_a_mepb): +class LifterModelCallMepl(Lifter_MEPl, LifterModelCallMepb): """MeP high level IR manipulations - Little Endian""" def __init__(self, loc_db): - ir_a_mepb.__init__(self, loc_db) + LifterModelCallMepb.__init__(self, loc_db) diff --git a/miasm/arch/mep/sem.py b/miasm/arch/mep/sem.py index 221d18f8..0ac50c58 100644 --- a/miasm/arch/mep/sem.py +++ b/miasm/arch/mep/sem.py @@ -2,7 +2,7 @@ # Guillaume Valadon <guillaume@valadon.net> from miasm.core.sembuilder import SemBuilder -from miasm.ir.ir import IntermediateRepresentation +from miasm.ir.ir import Lifter from miasm.arch.mep.arch import mn_mep from miasm.arch.mep.regs import PC, SP, LP, SAR, TP, RPB, RPE, RPC, EPC, NPC, \ take_jmp, in_erepeat @@ -494,7 +494,7 @@ def sll3(r0, rn, imm5): @sbuild.parse def fsft(rn, rm): - "FSFT - Funnel shift.""" + """FSFT - Funnel shift.""" # Rn <- ((Rn||Rm)<<SAR5..0)63..32 # Note: lowest Rm bits are discarded @@ -1199,7 +1199,7 @@ def get_mnemo_expr(ir, instr, *args): return ir, extra_ir -class ir_mepb(IntermediateRepresentation): +class Lifter_MEPb(Lifter): """Toshiba MeP miasm IR - Big Endian It transforms an instructon into an IR. @@ -1208,7 +1208,7 @@ class ir_mepb(IntermediateRepresentation): addrsize = 32 def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_mep, "b", loc_db) + Lifter.__init__(self, mn_mep, "b", loc_db) self.pc = mn_mep.getpc() self.sp = mn_mep.getsp() self.IRDst = ExprId("IRDst", 32) @@ -1230,11 +1230,11 @@ class ir_mepb(IntermediateRepresentation): return l -class ir_mepl(ir_mepb): +class Lifter_MEPl(Lifter_MEPb): """Toshiba MeP miasm IR - Little Endian""" def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_mep, "l", loc_db) + Lifter.__init__(self, mn_mep, "l", loc_db) self.pc = mn_mep.getpc() self.sp = mn_mep.getsp() self.IRDst = ExprId("IRDst", 32) diff --git a/miasm/arch/mips32/jit.py b/miasm/arch/mips32/jit.py index d8bd8c66..779c2b77 100644 --- a/miasm/arch/mips32/jit.py +++ b/miasm/arch/mips32/jit.py @@ -4,7 +4,7 @@ import logging from miasm.jitter.jitload import Jitter, named_arguments from miasm.core.locationdb import LocationDB from miasm.core.utils import pck32, upck32 -from miasm.arch.mips32.sem import ir_mips32l, ir_mips32b +from miasm.arch.mips32.sem import Lifter_Mips32l, Lifter_Mips32b from miasm.jitter.codegen import CGen from miasm.ir.ir import AssignBlock, IRBlock import miasm.expression.expression as m2_expr @@ -86,7 +86,7 @@ class jitter_mips32l(Jitter): C_Gen = mipsCGen def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_mips32l(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_Mips32l(loc_db), *args, **kwargs) self.vm.set_little_endian() def push_uint32_t(self, value): @@ -145,5 +145,5 @@ class jitter_mips32l(Jitter): class jitter_mips32b(jitter_mips32l): def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_mips32b(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_Mips32b(loc_db), *args, **kwargs) self.vm.set_big_endian() diff --git a/miasm/arch/mips32/ira.py b/miasm/arch/mips32/lifter_model_call.py index e57e3a36..bd0e8506 100644 --- a/miasm/arch/mips32/ira.py +++ b/miasm/arch/mips32/lifter_model_call.py @@ -2,12 +2,12 @@ from miasm.expression.expression import ExprAssign, ExprOp from miasm.ir.ir import IRBlock, AssignBlock -from miasm.ir.analysis import ira -from miasm.arch.mips32.sem import ir_mips32l, ir_mips32b +from miasm.ir.analysis import LifterModelCall +from miasm.arch.mips32.sem import Lifter_Mips32l, Lifter_Mips32b -class ir_a_mips32l(ir_mips32l, ira): +class LifterModelCallMips32l(Lifter_Mips32l, LifterModelCall): def __init__(self, loc_db): - ir_mips32l.__init__(self, loc_db) + Lifter_Mips32l.__init__(self, loc_db) self.ret_reg = self.arch.regs.V0 def call_effects(self, ad, instr): @@ -98,7 +98,7 @@ class ir_a_mips32l(ir_mips32l, ira): -class ir_a_mips32b(ir_mips32b, ir_a_mips32l): +class LifterModelCallMips32b(Lifter_Mips32b, LifterModelCallMips32l): def __init__(self, loc_db): - ir_mips32b.__init__(self, loc_db) + Lifter_Mips32b.__init__(self, loc_db) self.ret_reg = self.arch.regs.V0 diff --git a/miasm/arch/mips32/sem.py b/miasm/arch/mips32/sem.py index 65af7a38..92302fa1 100644 --- a/miasm/arch/mips32/sem.py +++ b/miasm/arch/mips32/sem.py @@ -1,5 +1,5 @@ import miasm.expression.expression as m2_expr -from miasm.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock +from miasm.ir.ir import Lifter, IRBlock, AssignBlock from miasm.arch.mips32.arch import mn_mips32 from miasm.arch.mips32.regs import R_LO, R_HI, PC, RA, ZERO, exception_flags from miasm.core.sembuilder import SemBuilder @@ -618,10 +618,10 @@ def get_mnemo_expr(ir, instr, *args): instr, extra_ir = mnemo_func[instr.name.lower()](ir, instr, *args) return instr, extra_ir -class ir_mips32l(IntermediateRepresentation): +class Lifter_Mips32l(Lifter): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_mips32, 'l', loc_db) + Lifter.__init__(self, mn_mips32, 'l', loc_db) self.pc = mn_mips32.getpc() self.sp = mn_mips32.getsp() self.IRDst = m2_expr.ExprId('IRDst', 32) @@ -652,10 +652,10 @@ class ir_mips32l(IntermediateRepresentation): def get_next_delay_loc_key(self, instr): return self.loc_db.get_or_create_offset_location(instr.offset + 16) -class ir_mips32b(ir_mips32l): +class Lifter_Mips32b(Lifter_Mips32l): def __init__(self, loc_db): self.addrsize = 32 - IntermediateRepresentation.__init__(self, mn_mips32, 'b', loc_db) + Lifter.__init__(self, mn_mips32, 'b', loc_db) self.pc = mn_mips32.getpc() self.sp = mn_mips32.getsp() self.IRDst = m2_expr.ExprId('IRDst', 32) diff --git a/miasm/arch/msp430/jit.py b/miasm/arch/msp430/jit.py index 1212b338..ad767588 100644 --- a/miasm/arch/msp430/jit.py +++ b/miasm/arch/msp430/jit.py @@ -1,7 +1,7 @@ from miasm.jitter.jitload import Jitter from miasm.core.locationdb import LocationDB from miasm.core.utils import pck16, upck16 -from miasm.arch.msp430.sem import ir_msp430 +from miasm.arch.msp430.sem import Lifter_MSP430 import logging @@ -14,7 +14,7 @@ log.setLevel(logging.CRITICAL) class jitter_msp430(Jitter): def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_msp430(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_MSP430(loc_db), *args, **kwargs) self.vm.set_little_endian() def push_uint16_t(self, value): diff --git a/miasm/arch/msp430/ira.py b/miasm/arch/msp430/lifter_model_call.py index 264de12c..05f649e5 100644 --- a/miasm/arch/msp430/ira.py +++ b/miasm/arch/msp430/lifter_model_call.py @@ -1,14 +1,14 @@ #-*- coding:utf-8 -*- -from miasm.ir.analysis import ira -from miasm.arch.msp430.sem import ir_msp430 +from miasm.ir.analysis import LifterModelCall +from miasm.arch.msp430.sem import Lifter_MSP430 from miasm.ir.ir import AssignBlock from miasm.expression.expression import * -class ir_a_msp430_base(ir_msp430, ira): +class LifterModelCallMsp430Base(Lifter_MSP430, LifterModelCall): def __init__(self, loc_db): - ir_msp430.__init__(self, loc_db) + Lifter_MSP430.__init__(self, loc_db) self.ret_reg = self.arch.regs.R15 def call_effects(self, addr, instr): @@ -21,10 +21,10 @@ class ir_a_msp430_base(ir_msp430, ira): ) return [call_assignblk], [] -class ir_a_msp430(ir_a_msp430_base): +class LifterModelCallMsp430(LifterModelCallMsp430Base): def __init__(self, loc_db): - ir_a_msp430_base.__init__(self, loc_db) + LifterModelCallMsp430Base.__init__(self, loc_db) def get_out_regs(self, _): return set([self.ret_reg, self.sp]) diff --git a/miasm/arch/msp430/sem.py b/miasm/arch/msp430/sem.py index 196e09f1..d4d3221b 100644 --- a/miasm/arch/msp430/sem.py +++ b/miasm/arch/msp430/sem.py @@ -3,7 +3,7 @@ from miasm.expression.expression import * from miasm.arch.msp430.regs import * from miasm.arch.msp430.arch import mn_msp430 -from miasm.ir.ir import IntermediateRepresentation +from miasm.ir.ir import Lifter # Utils @@ -473,10 +473,10 @@ def ComposeExprAssign(dst, src): return e -class ir_msp430(IntermediateRepresentation): +class Lifter_MSP430(Lifter): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_msp430, None, loc_db) + Lifter.__init__(self, mn_msp430, None, loc_db) self.pc = PC self.sp = SP self.IRDst = ExprId('IRDst', 16) diff --git a/miasm/arch/ppc/jit.py b/miasm/arch/ppc/jit.py index ccdaab72..dcaff82c 100644 --- a/miasm/arch/ppc/jit.py +++ b/miasm/arch/ppc/jit.py @@ -1,6 +1,6 @@ from builtins import range from miasm.jitter.jitload import Jitter, named_arguments -from miasm.arch.ppc.sem import ir_ppc32b +from miasm.arch.ppc.sem import Lifter_PPC32b import struct import logging @@ -15,7 +15,7 @@ class jitter_ppc32b(Jitter): max_reg_arg = 8 def __init__(self, loc_db, *args, **kwargs): - super(jitter_ppc32b, self).__init__(ir_ppc32b(loc_db), + super(jitter_ppc32b, self).__init__(Lifter_PPC32b(loc_db), *args, **kwargs) self.vm.set_big_endian() diff --git a/miasm/arch/ppc/ira.py b/miasm/arch/ppc/lifter_model_call.py index 72bf7d7c..06691190 100644 --- a/miasm/arch/ppc/ira.py +++ b/miasm/arch/ppc/lifter_model_call.py @@ -1,13 +1,13 @@ from miasm.expression.expression import ExprAssign, ExprOp from miasm.ir.ir import AssignBlock -from miasm.ir.analysis import ira -from miasm.arch.ppc.sem import ir_ppc32b +from miasm.ir.analysis import LifterModelCall +from miasm.arch.ppc.sem import Lifter_PPC32b -class ir_a_ppc32b(ir_ppc32b, ira): +class LifterModelCallPpc32b(Lifter_PPC32b, LifterModelCall): def __init__(self, loc_db, *args): - super(ir_a_ppc32b, self).__init__(loc_db, *args) + super(LifterModelCallPpc32b, self).__init__(loc_db, *args) self.ret_reg = self.arch.regs.R3 # for test XXX TODO diff --git a/miasm/arch/ppc/sem.py b/miasm/arch/ppc/sem.py index 6d18777c..7fbf61e6 100644 --- a/miasm/arch/ppc/sem.py +++ b/miasm/arch/ppc/sem.py @@ -2,7 +2,7 @@ from __future__ import print_function from builtins import range import miasm.expression.expression as expr -from miasm.ir.ir import AssignBlock, IntermediateRepresentation, IRBlock +from miasm.ir.ir import AssignBlock, Lifter, IRBlock from miasm.arch.ppc.arch import mn_ppc from miasm.arch.ppc.regs import * from miasm.core.sembuilder import SemBuilder @@ -897,10 +897,10 @@ sem_dir = { } -class ir_ppc32b(IntermediateRepresentation): +class Lifter_PPC32b(Lifter): def __init__(self, loc_db): - super(ir_ppc32b, self).__init__(mn_ppc, 'b', loc_db) + super(Lifter_PPC32b, self).__init__(mn_ppc, 'b', loc_db) self.pc = mn_ppc.getpc() self.sp = mn_ppc.getsp() self.IRDst = expr.ExprId('IRDst', 32) diff --git a/miasm/arch/x86/jit.py b/miasm/arch/x86/jit.py index 9113b9ad..38301e3c 100644 --- a/miasm/arch/x86/jit.py +++ b/miasm/arch/x86/jit.py @@ -2,7 +2,7 @@ from builtins import range import logging from miasm.jitter.jitload import Jitter, named_arguments -from miasm.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 +from miasm.arch.x86.sem import Lifter_X86_16, Lifter_X86_32, Lifter_X86_64 from miasm.jitter.codegen import CGen from miasm.ir.translators.C import TranslatorC @@ -42,7 +42,7 @@ class jitter_x86_16(Jitter): C_Gen = x86_32_CGen def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_x86_16(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_X86_16(loc_db), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode @@ -73,7 +73,7 @@ class jitter_x86_32(Jitter): C_Gen = x86_32_CGen def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_x86_32(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_X86_32(loc_db), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False @@ -199,7 +199,7 @@ class jitter_x86_64(Jitter): args_regs_stdcall = ['RCX', 'RDX', 'R8', 'R9'] def __init__(self, loc_db, *args, **kwargs): - Jitter.__init__(self, ir_x86_64(loc_db), *args, **kwargs) + Jitter.__init__(self, Lifter_X86_64(loc_db), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False diff --git a/miasm/arch/x86/ira.py b/miasm/arch/x86/lifter_model_call.py index 1615622b..e75f8c69 100644 --- a/miasm/arch/x86/ira.py +++ b/miasm/arch/x86/lifter_model_call.py @@ -2,23 +2,23 @@ from miasm.expression.expression import ExprAssign, ExprOp from miasm.ir.ir import AssignBlock -from miasm.ir.analysis import ira -from miasm.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 +from miasm.ir.analysis import LifterModelCall +from miasm.arch.x86.sem import Lifter_X86_16, Lifter_X86_32, Lifter_X86_64 -class ir_a_x86_16(ir_x86_16, ira): +class LifterModelCall_x86_16(Lifter_X86_16, LifterModelCall): def __init__(self, loc_db): - ir_x86_16.__init__(self, loc_db) + Lifter_X86_16.__init__(self, loc_db) self.ret_reg = self.arch.regs.AX def get_out_regs(self, _): return set([self.ret_reg, self.sp]) -class ir_a_x86_32(ir_x86_32, ir_a_x86_16): +class LifterModelCall_x86_32(Lifter_X86_32, LifterModelCall_x86_16): def __init__(self, loc_db): - ir_x86_32.__init__(self, loc_db) + Lifter_X86_32.__init__(self, loc_db) self.ret_reg = self.arch.regs.EAX def sizeof_char(self): @@ -37,10 +37,10 @@ class ir_a_x86_32(ir_x86_32, ir_a_x86_16): return 32 -class ir_a_x86_64(ir_x86_64, ir_a_x86_16): +class LifterModelCall_x86_64(Lifter_X86_64, LifterModelCall_x86_16): def __init__(self, loc_db): - ir_x86_64.__init__(self, loc_db) + Lifter_X86_64.__init__(self, loc_db) self.ret_reg = self.arch.regs.RAX def call_effects(self, ad, instr): diff --git a/miasm/arch/x86/sem.py b/miasm/arch/x86/sem.py index 45eb5135..5b6ff917 100644 --- a/miasm/arch/x86/sem.py +++ b/miasm/arch/x86/sem.py @@ -25,7 +25,7 @@ import miasm.expression.expression as m2_expr from miasm.expression.simplifications import expr_simp from miasm.arch.x86.regs import * from miasm.arch.x86.arch import mn_x86, repeat_mn, replace_regs, is_mem_segm -from miasm.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock +from miasm.ir.ir import Lifter, IRBlock, AssignBlock from miasm.core.sembuilder import SemBuilder from miasm.jitter.csts import EXCEPT_DIV_BY_ZERO, EXCEPT_ILLEGAL_INSN, \ EXCEPT_PRIV_INSN, EXCEPT_SOFT_BP, EXCEPT_INT_XX, EXCEPT_INT_1, \ @@ -5748,10 +5748,10 @@ mnemo_func = {'mov': mov, } -class ir_x86_16(IntermediateRepresentation): +class Lifter_X86_16(Lifter): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_x86, 16, loc_db) + Lifter.__init__(self, mn_x86, 16, loc_db) self.do_stk_segm = False self.do_ds_segm = False self.do_str_segm = False @@ -5891,10 +5891,10 @@ class ir_x86_16(IntermediateRepresentation): return IRBlock(self.loc_db, irblock.loc_key, irs) -class ir_x86_32(ir_x86_16): +class Lifter_X86_32(Lifter_X86_16): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_x86, 32, loc_db) + Lifter.__init__(self, mn_x86, 32, loc_db) self.do_stk_segm = False self.do_ds_segm = False self.do_str_segm = False @@ -5905,10 +5905,10 @@ class ir_x86_32(ir_x86_16): self.addrsize = 32 -class ir_x86_64(ir_x86_16): +class Lifter_X86_64(Lifter_X86_16): def __init__(self, loc_db): - IntermediateRepresentation.__init__(self, mn_x86, 64, loc_db) + Lifter.__init__(self, mn_x86, 64, loc_db) self.do_stk_segm = False self.do_ds_segm = False self.do_str_segm = False diff --git a/miasm/ir/analysis.py b/miasm/ir/analysis.py index 9aa61f59..c08ea13b 100644 --- a/miasm/ir/analysis.py +++ b/miasm/ir/analysis.py @@ -3,7 +3,7 @@ import warnings import logging -from miasm.ir.ir import IntermediateRepresentation, AssignBlock +from miasm.ir.ir import Lifter, AssignBlock from miasm.expression.expression import ExprOp, ExprAssign @@ -14,16 +14,16 @@ log.addHandler(console_handler) log.setLevel(logging.WARNING) -class ira(IntermediateRepresentation): +class LifterModelCall(Lifter): """IR Analysis This class provides higher level manipulations on IR, such as dead instruction removals. This class can be used as a common parent with - `miasm.ir.ir::IntermediateRepresentation` class. + `miasm.ir.ir::Lifter` class. For instance: - class ira_x86_16(ir_x86_16, ira) + class LifterModelCall_x86_16(Lifter_X86_16, LifterModelCall) """ ret_reg = None @@ -105,3 +105,15 @@ class ira(IntermediateRepresentation): def sizeof_pointer(self): "Return the size of a void* in bits" raise NotImplementedError("Abstract method") + + + +class ira(LifterModelCall): + """ + DEPRECATED object + Use LifterModelCall instead of ira + """ + + def __init__(self, arch, attrib, loc_db): + warnings.warn('DEPRECATION WARNING: use "LifterModelCall" instead of "ira"') + super(ira, self).__init__(arch, attrib, loc_db) diff --git a/miasm/ir/ir.py b/miasm/ir/ir.py index aed5cb65..9039efa1 100644 --- a/miasm/ir/ir.py +++ b/miasm/ir/ir.py @@ -706,7 +706,7 @@ class DiGraphIR(IRCFG): raise NotImplementedError("Deprecated") -class IntermediateRepresentation(object): +class Lifter(object): """ Intermediate representation object @@ -837,7 +837,7 @@ class IntermediateRepresentation(object): Use add_asmblock_to_ircfg instead of add_block """ warnings.warn("""DEPRECATION WARNING - ircfg is now out of IntermediateRepresentation + ircfg is now out of Lifter Use: ircfg = ir_arch.new_ircfg() ir_arch.add_asmblock_to_ircfg(block, ircfg) @@ -921,12 +921,23 @@ class IntermediateRepresentation(object): return new_irblocks -class ir(IntermediateRepresentation): +class IntermediateRepresentation(Lifter): """ DEPRECATED object - Use IntermediateRepresentation instead of ir + Use Lifter instead of IntermediateRepresentation + """ + + def __init__(self, arch, attrib, loc_db): + warnings.warn('DEPRECATION WARNING: use "Lifter" instead of "IntermediateRepresentation"') + super(IntermediateRepresentation, self).__init__(arch, attrib, loc_db) + + +class ir(Lifter): + """ + DEPRECATED object + Use Lifter instead of ir """ def __init__(self, loc_key, irs, lines=None): - warnings.warn('DEPRECATION WARNING: use "IntermediateRepresentation" instead of "ir"') + warnings.warn('DEPRECATION WARNING: use "Lifter" instead of "ir"') super(ir, self).__init__(loc_key, irs, lines) diff --git a/miasm/ir/symbexec.py b/miasm/ir/symbexec.py index 8c6245b8..ee8e4924 100644 --- a/miasm/ir/symbexec.py +++ b/miasm/ir/symbexec.py @@ -764,7 +764,7 @@ class SymbolicExecutionEngine(object): from miasm.ir.symbexec import SymbolicExecutionEngine from miasm.ir.ir import AssignBlock - ir_arch = ir_x86_32() + ir_arch = Lifter_X86_32() init_state = { ir_arch.arch.regs.EAX: ir_arch.arch.regs.EBX, diff --git a/miasm/jitter/arch/JitCore_mips32.c b/miasm/jitter/arch/JitCore_mips32.c index dc576dfb..1d7a762c 100644 --- a/miasm/jitter/arch/JitCore_mips32.c +++ b/miasm/jitter/arch/JitCore_mips32.c @@ -185,6 +185,11 @@ PyObject * cpu_dump_gpregs(JitCpu* self, PyObject* args) return Py_None; } +PyObject * cpu_dump_gpregs_with_attrib(JitCpu* self, PyObject* args) +{ + return cpu_dump_gpregs(self, args); +} + PyObject* cpu_set_exception(JitCpu* self, PyObject* args) { @@ -238,6 +243,8 @@ static PyMethodDef JitCpu_methods[] = { "X"}, {"dump_gpregs", (PyCFunction)cpu_dump_gpregs, METH_NOARGS, "X"}, + {"dump_gpregs_with_attrib", (PyCFunction)cpu_dump_gpregs_with_attrib, METH_VARARGS, + "X"}, {"get_gpreg", (PyCFunction)cpu_get_gpreg, METH_NOARGS, "X"}, {"set_gpreg", (PyCFunction)cpu_set_gpreg, METH_VARARGS, diff --git a/miasm/jitter/llvmconvert.py b/miasm/jitter/llvmconvert.py index 5aae624b..2430d884 100644 --- a/miasm/jitter/llvmconvert.py +++ b/miasm/jitter/llvmconvert.py @@ -17,6 +17,7 @@ import os from llvmlite import binding as llvm from llvmlite import ir as llvm_ir from builtins import int as int_types +import warnings from future.utils import viewitems, viewvalues @@ -221,15 +222,20 @@ class LLVMContext_JIT(LLVMContext): """Extend LLVMContext_JIT in order to handle memory management and custom operations""" - def __init__(self, library_filenames, ir_arch, name="mod"): + def __init__(self, library_filenames, lifter, name="mod"): "Init a LLVMContext object, and load the mem management shared library" self.library_filenames = library_filenames - self.ir_arch = ir_arch + self.lifter = lifter self.arch_specific() self.load_libraries() LLVMContext.__init__(self, name) self.vmcpu = {} + @property + def ir_arch(self): + warnings.warn('DEPRECATION WARNING: use ".lifter" instead of ".ir_arch"') + return self.lifter + def load_libraries(self): # Get LLVM specific functions name = "libLLVM-%d.%d" % (llvm.llvm_version_info[0], @@ -256,12 +262,12 @@ class LLVMContext_JIT(LLVMContext): self.add_log_functions() def arch_specific(self): - arch = self.ir_arch.arch + arch = self.lifter.arch if arch.name == "x86": self.PC = arch.regs.RIP - self.logging_func = "dump_gpregs_%d" % self.ir_arch.attrib + self.logging_func = "dump_gpregs_%d" % self.lifter.attrib else: - self.PC = self.ir_arch.pc + self.PC = self.lifter.pc self.logging_func = "dump_gpregs" if arch.name == "mips32": from miasm.arch.mips32.jit import mipsCGen @@ -774,7 +780,7 @@ class LLVMFunction(object): return ret if expr.is_loc(): - offset = self.llvm_context.ir_arch.loc_db.get_location_offset( + offset = self.llvm_context.lifter.loc_db.get_location_offset( expr.loc_key ) ret = llvm_ir.Constant(LLVMType.IntType(expr.size), offset) @@ -1365,7 +1371,7 @@ class LLVMFunction(object): # Get exception flag value builder = self.builder - m2_exception_flag = self.llvm_context.ir_arch.arch.regs.exception_flags + m2_exception_flag = self.llvm_context.lifter.arch.regs.exception_flags t_size = LLVMType.IntType(m2_exception_flag.size) exceptionflag = self.add_ir(m2_exception_flag) @@ -1411,7 +1417,7 @@ class LLVMFunction(object): def gen_pre_code(self, instr_attrib): if instr_attrib.log_mn: - loc_db = self.llvm_context.ir_arch.loc_db + loc_db = self.llvm_context.lifter.loc_db self.printf( "%.8X %s\n" % ( instr_attrib.instr.offset, @@ -1489,13 +1495,13 @@ class LLVMFunction(object): offset = None if isinstance(dst, ExprInt): offset = int(dst) - loc_key = self.llvm_context.ir_arch.loc_db.get_or_create_offset_location(offset) + loc_key = self.llvm_context.lifter.loc_db.get_or_create_offset_location(offset) dst = ExprLoc(loc_key, dst.size) if isinstance(dst, ExprLoc): loc_key = dst.loc_key bbl = self.get_basic_block_by_loc_key(loc_key) - offset = self.llvm_context.ir_arch.loc_db.get_location_offset(loc_key) + offset = self.llvm_context.lifter.loc_db.get_location_offset(loc_key) if bbl is not None: # "local" jump, inside this function if offset is None: @@ -1557,7 +1563,7 @@ class LLVMFunction(object): # Evaluate expressions values = {} for dst, src in viewitems(assignblk): - if dst == self.llvm_context.ir_arch.IRDst: + if dst == self.llvm_context.lifter.IRDst: case2dst, case_value = self.expr2cases(src) else: values[dst] = self.add_ir(src) @@ -1629,7 +1635,7 @@ class LLVMFunction(object): Translate an asm_bad_block into a CPU exception """ builder = self.builder - m2_exception_flag = self.llvm_context.ir_arch.arch.regs.exception_flags + m2_exception_flag = self.llvm_context.lifter.arch.regs.exception_flags t_size = LLVMType.IntType(m2_exception_flag.size) self.assign( self.add_ir(ExprInt(1, 8)), @@ -1639,7 +1645,7 @@ class LLVMFunction(object): t_size(m2_csts.EXCEPT_UNK_MNEMO), m2_exception_flag ) - offset = self.llvm_context.ir_arch.loc_db.get_location_offset( + offset = self.llvm_context.lifter.loc_db.get_location_offset( asmblock.loc_key ) self.set_ret(LLVMType.IntType(64)(offset)) @@ -1689,7 +1695,7 @@ class LLVMFunction(object): # Else Block builder.position_at_end(else_block) PC = self.llvm_context.PC - next_label_offset = self.llvm_context.ir_arch.loc_db.get_location_offset(next_label) + next_label_offset = self.llvm_context.lifter.loc_db.get_location_offset(next_label) to_ret = LLVMType.IntType(PC.size)(next_label_offset) self.assign(to_ret, PC) self.set_ret(to_ret) @@ -1726,11 +1732,11 @@ class LLVMFunction(object): # Create basic blocks (for label branches) entry_bbl, builder = self.entry_bbl, self.builder for instr in asmblock.lines: - lbl = self.llvm_context.ir_arch.loc_db.get_or_create_offset_location(instr.offset) + lbl = self.llvm_context.lifter.loc_db.get_or_create_offset_location(instr.offset) self.append_basic_block(lbl) # TODO: merge duplicate code with CGen - codegen = self.llvm_context.cgen_class(self.llvm_context.ir_arch) + codegen = self.llvm_context.cgen_class(self.llvm_context.lifter) irblocks_list = codegen.block2assignblks(asmblock) instr_offsets = [line.offset for line in asmblock.lines] @@ -1744,7 +1750,7 @@ class LLVMFunction(object): ) self.local_vars_pointers[element.name] = ptr loc_key = codegen.get_block_post_label(asmblock) - offset = self.llvm_context.ir_arch.loc_db.get_location_offset(loc_key) + offset = self.llvm_context.lifter.loc_db.get_location_offset(loc_key) instr_offsets.append(offset) self.append_basic_block(loc_key) @@ -1766,8 +1772,8 @@ class LLVMFunction(object): # Generate the corresponding code for index, irblock in enumerate(irblocks): - new_irblock = self.llvm_context.ir_arch.irbloc_fix_regs_for_mode( - irblock, self.llvm_context.ir_arch.attrib) + new_irblock = self.llvm_context.lifter.irbloc_fix_regs_for_mode( + irblock, self.llvm_context.lifter.attrib) # Set the builder at the beginning of the correct bbl self.builder.position_at_end(self.get_basic_block_by_loc_key(new_irblock.loc_key)) @@ -1848,7 +1854,7 @@ class LLVMFunction_IRCompilation(LLVMFunction): Example of use: >>> context = LLVMContext_IRCompilation() - >>> context.ir_arch = ir + >>> context.lifter = lifter >>> >>> func = LLVMFunction_IRCompilation(context, name="test") >>> func.ret_type = llvm_ir.VoidType() @@ -1866,7 +1872,7 @@ class LLVMFunction_IRCompilation(LLVMFunction): super(LLVMFunction_IRCompilation, self).init_fc() # Create a global IRDst if not any - IRDst = self.llvm_context.ir_arch.IRDst + IRDst = self.llvm_context.lifter.IRDst if str(IRDst) not in self.mod.globals: llvm_ir.GlobalVariable(self.mod, LLVMType.IntType(IRDst.size), name=str(IRDst)) @@ -1879,7 +1885,7 @@ class LLVMFunction_IRCompilation(LLVMFunction): if isinstance(dst, Expr): if dst.is_int(): - loc = self.llvm_context.ir_arch.loc_db.getby_offset_create(int(dst)) + loc = self.llvm_context.lifter.loc_db.getby_offset_create(int(dst)) dst = ExprLoc(loc, dst.size) assert dst.is_loc() bbl = self.get_basic_block_by_loc_key(dst.loc_key) diff --git a/test/analysis/data_flow.py b/test/analysis/data_flow.py index 840bf9ce..6a3c2ce7 100644 --- a/test/analysis/data_flow.py +++ b/test/analysis/data_flow.py @@ -6,7 +6,7 @@ from future.utils import viewitems from miasm.expression.expression import ExprId, ExprInt, ExprAssign, ExprMem from miasm.core.locationdb import LocationDB from miasm.analysis.data_flow import DeadRemoval, ReachingDefinitions, DiGraphDefUse -from miasm.ir.analysis import ira +from miasm.ir.analysis import LifterModelCall from miasm.ir.ir import IRBlock, AssignBlock loc_db = LocationDB() @@ -68,99 +68,99 @@ class Arch(object): def getsp(self, _): return sp -class IRATest(ira): +class LifterTest(LifterModelCall): - """Fake IRA class for tests""" + """Fake Lifter class for tests""" def __init__(self, loc_db): arch = Arch() - super(IRATest, self).__init__(arch, 32, loc_db) + super(LifterTest, self).__init__(arch, 32, loc_db) self.IRDst = IRDst self.ret_reg = r def get_out_regs(self, _): return set([self.ret_reg, self.sp]) -IRA = IRATest(loc_db) -deadrm = DeadRemoval(IRA) +Lifter = LifterTest(loc_db) +deadrm = DeadRemoval(Lifter) # graph 1 : Simple graph with dead and alive variables -G1_IRA = IRA.new_ircfg() +G1_cfg = Lifter.new_ircfg() G1_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)], [ExprAssign(b, CST2)]]) G1_IRB1 = gen_irblock(LBL1, [[ExprAssign(a, b)]]) G1_IRB2 = gen_irblock(LBL2, [[ExprAssign(r, a)]]) for irb in [G1_IRB0, G1_IRB1, G1_IRB2]: - G1_IRA.add_irblock(irb) + G1_cfg.add_irblock(irb) -G1_IRA.add_uniq_edge(G1_IRB0.loc_key, G1_IRB1.loc_key) -G1_IRA.add_uniq_edge(G1_IRB1.loc_key, G1_IRB2.loc_key) +G1_cfg.add_uniq_edge(G1_IRB0.loc_key, G1_IRB1.loc_key) +G1_cfg.add_uniq_edge(G1_IRB1.loc_key, G1_IRB2.loc_key) # Expected output for graph 1 -G1_EXP_IRA = IRA.new_ircfg() +G1_EXP_cfg = Lifter.new_ircfg() G1_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAssign(b, CST2)]]) G1_EXP_IRB1 = gen_irblock(LBL1, [[ExprAssign(a, b)]]) G1_EXP_IRB2 = gen_irblock(LBL2, [[ExprAssign(r, a)]]) for irb in [G1_EXP_IRB0, G1_EXP_IRB1, G1_EXP_IRB2]: - G1_EXP_IRA.add_irblock(irb) + G1_EXP_cfg.add_irblock(irb) # graph 2 : Natural loop with dead variable -G2_IRA = IRA.new_ircfg() +G2_cfg = Lifter.new_ircfg() G2_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)], [ExprAssign(r, CST1)]]) G2_IRB1 = gen_irblock(LBL1, [[ExprAssign(a, a+CST1)]]) G2_IRB2 = gen_irblock(LBL2, [[ExprAssign(a, r)]]) for irb in [G2_IRB0, G2_IRB1, G2_IRB2]: - G2_IRA.add_irblock(irb) + G2_cfg.add_irblock(irb) -G2_IRA.add_uniq_edge(G2_IRB0.loc_key, G2_IRB1.loc_key) -G2_IRA.add_uniq_edge(G2_IRB1.loc_key, G2_IRB2.loc_key) -G2_IRA.add_uniq_edge(G2_IRB1.loc_key, G2_IRB1.loc_key) +G2_cfg.add_uniq_edge(G2_IRB0.loc_key, G2_IRB1.loc_key) +G2_cfg.add_uniq_edge(G2_IRB1.loc_key, G2_IRB2.loc_key) +G2_cfg.add_uniq_edge(G2_IRB1.loc_key, G2_IRB1.loc_key) # Expected output for graph 2 -G2_EXP_IRA = IRA.new_ircfg() +G2_EXP_cfg = Lifter.new_ircfg() G2_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAssign(r, CST1)]]) G2_EXP_IRB1 = gen_irblock(LBL1, [[]]) G2_EXP_IRB2 = gen_irblock(LBL2, [[]]) for irb in [G2_EXP_IRB0, G2_EXP_IRB1, G2_EXP_IRB2]: - G2_EXP_IRA.add_irblock(irb) + G2_EXP_cfg.add_irblock(irb) # graph 3 : Natural loop with alive variables -G3_IRA = IRA.new_ircfg() +G3_cfg = Lifter.new_ircfg() G3_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)]]) G3_IRB1 = gen_irblock(LBL1, [[ExprAssign(a, a+CST1)]]) G3_IRB2 = gen_irblock(LBL2, [[ExprAssign(r, a)]]) for irb in [G3_IRB0, G3_IRB1, G3_IRB2]: - G3_IRA.add_irblock(irb) + G3_cfg.add_irblock(irb) -G3_IRA.add_uniq_edge(G3_IRB0.loc_key, G3_IRB1.loc_key) -G3_IRA.add_uniq_edge(G3_IRB1.loc_key, G3_IRB2.loc_key) -G3_IRA.add_uniq_edge(G3_IRB1.loc_key, G3_IRB1.loc_key) +G3_cfg.add_uniq_edge(G3_IRB0.loc_key, G3_IRB1.loc_key) +G3_cfg.add_uniq_edge(G3_IRB1.loc_key, G3_IRB2.loc_key) +G3_cfg.add_uniq_edge(G3_IRB1.loc_key, G3_IRB1.loc_key) # Expected output for graph 3 -G3_EXP_IRA = IRA.new_ircfg() +G3_EXP_cfg = Lifter.new_ircfg() G3_EXP_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)]]) G3_EXP_IRB1 = gen_irblock(LBL1, [[ExprAssign(a, a+CST1)]]) G3_EXP_IRB2 = gen_irblock(LBL2, [[ExprAssign(r, a)]]) for irb in [G3_EXP_IRB0, G3_EXP_IRB1, G3_EXP_IRB2]: - G3_EXP_IRA.add_irblock(irb) + G3_EXP_cfg.add_irblock(irb) # graph 4 : If/else with dead variables -G4_IRA = IRA.new_ircfg() +G4_cfg = Lifter.new_ircfg() G4_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)]]) G4_IRB1 = gen_irblock(LBL1, [[ExprAssign(a, a+CST1)]]) @@ -168,15 +168,15 @@ G4_IRB2 = gen_irblock(LBL2, [[ExprAssign(a, a+CST2)]]) G4_IRB3 = gen_irblock(LBL3, [[ExprAssign(a, CST3)], [ExprAssign(r, a)]]) for irb in [G4_IRB0, G4_IRB1, G4_IRB2, G4_IRB3]: - G4_IRA.add_irblock(irb) + G4_cfg.add_irblock(irb) -G4_IRA.add_uniq_edge(G4_IRB0.loc_key, G4_IRB1.loc_key) -G4_IRA.add_uniq_edge(G4_IRB0.loc_key, G4_IRB2.loc_key) -G4_IRA.add_uniq_edge(G4_IRB1.loc_key, G4_IRB3.loc_key) -G4_IRA.add_uniq_edge(G4_IRB2.loc_key, G4_IRB3.loc_key) +G4_cfg.add_uniq_edge(G4_IRB0.loc_key, G4_IRB1.loc_key) +G4_cfg.add_uniq_edge(G4_IRB0.loc_key, G4_IRB2.loc_key) +G4_cfg.add_uniq_edge(G4_IRB1.loc_key, G4_IRB3.loc_key) +G4_cfg.add_uniq_edge(G4_IRB2.loc_key, G4_IRB3.loc_key) # Expected output for graph 4 -G4_EXP_IRA = IRA.new_ircfg() +G4_EXP_cfg = Lifter.new_ircfg() G4_EXP_IRB0 = gen_irblock(LBL0, [[]]) G4_EXP_IRB1 = gen_irblock(LBL1, [[]]) @@ -184,11 +184,11 @@ G4_EXP_IRB2 = gen_irblock(LBL2, [[]]) G4_EXP_IRB3 = gen_irblock(LBL3, [[ExprAssign(a, CST3)], [ExprAssign(r, a)]]) for irb in [G4_EXP_IRB0, G4_EXP_IRB1, G4_EXP_IRB2, G4_EXP_IRB3]: - G4_EXP_IRA.add_irblock(irb) + G4_EXP_cfg.add_irblock(irb) # graph 5 : Loop and If/else with dead variables -G5_IRA = IRA.new_ircfg() +G5_cfg = Lifter.new_ircfg() G5_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)]]) G5_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, CST2)]]) @@ -198,18 +198,18 @@ G5_IRB4 = gen_irblock(LBL4, [[ExprAssign(a, a+CST1)]]) G5_IRB5 = gen_irblock(LBL5, [[ExprAssign(a, r)]]) for irb in [G5_IRB0, G5_IRB1, G5_IRB2, G5_IRB3, G5_IRB4, G5_IRB5]: - G5_IRA.add_irblock(irb) + G5_cfg.add_irblock(irb) -G5_IRA.add_uniq_edge(G5_IRB0.loc_key, G5_IRB1.loc_key) -G5_IRA.add_uniq_edge(G5_IRB1.loc_key, G5_IRB2.loc_key) -G5_IRA.add_uniq_edge(G5_IRB1.loc_key, G5_IRB3.loc_key) -G5_IRA.add_uniq_edge(G5_IRB2.loc_key, G5_IRB4.loc_key) -G5_IRA.add_uniq_edge(G5_IRB3.loc_key, G5_IRB4.loc_key) -G5_IRA.add_uniq_edge(G5_IRB4.loc_key, G5_IRB5.loc_key) -G5_IRA.add_uniq_edge(G5_IRB4.loc_key, G5_IRB1.loc_key) +G5_cfg.add_uniq_edge(G5_IRB0.loc_key, G5_IRB1.loc_key) +G5_cfg.add_uniq_edge(G5_IRB1.loc_key, G5_IRB2.loc_key) +G5_cfg.add_uniq_edge(G5_IRB1.loc_key, G5_IRB3.loc_key) +G5_cfg.add_uniq_edge(G5_IRB2.loc_key, G5_IRB4.loc_key) +G5_cfg.add_uniq_edge(G5_IRB3.loc_key, G5_IRB4.loc_key) +G5_cfg.add_uniq_edge(G5_IRB4.loc_key, G5_IRB5.loc_key) +G5_cfg.add_uniq_edge(G5_IRB4.loc_key, G5_IRB1.loc_key) # Expected output for graph 5 -G5_EXP_IRA = IRA.new_ircfg() +G5_EXP_cfg = Lifter.new_ircfg() G5_EXP_IRB0 = gen_irblock(LBL0, [[]]) G5_EXP_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, CST2)]]) @@ -220,12 +220,12 @@ G5_EXP_IRB5 = gen_irblock(LBL5, [[]]) for irb in [G5_EXP_IRB0, G5_EXP_IRB1, G5_EXP_IRB2, G5_EXP_IRB3, G5_EXP_IRB4, G5_EXP_IRB5]: - G5_EXP_IRA.add_irblock(irb) + G5_EXP_cfg.add_irblock(irb) # graph 6 : Natural loop with dead variables symmetric assignment # (a = b <-> b = a ) -G6_IRA = IRA.new_ircfg() +G6_cfg = Lifter.new_ircfg() G6_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)]]) G6_IRB1 = gen_irblock(LBL1, [[ExprAssign(b, a)]]) @@ -233,15 +233,15 @@ G6_IRB2 = gen_irblock(LBL2, [[ExprAssign(a, b)]]) G6_IRB3 = gen_irblock(LBL3, [[ExprAssign(r, CST2)]]) for irb in [G6_IRB0, G6_IRB1, G6_IRB2, G6_IRB3]: - G6_IRA.add_irblock(irb) + G6_cfg.add_irblock(irb) -G6_IRA.add_uniq_edge(G6_IRB0.loc_key, G6_IRB1.loc_key) -G6_IRA.add_uniq_edge(G6_IRB1.loc_key, G6_IRB2.loc_key) -G6_IRA.add_uniq_edge(G6_IRB2.loc_key, G6_IRB1.loc_key) -G6_IRA.add_uniq_edge(G6_IRB2.loc_key, G6_IRB3.loc_key) +G6_cfg.add_uniq_edge(G6_IRB0.loc_key, G6_IRB1.loc_key) +G6_cfg.add_uniq_edge(G6_IRB1.loc_key, G6_IRB2.loc_key) +G6_cfg.add_uniq_edge(G6_IRB2.loc_key, G6_IRB1.loc_key) +G6_cfg.add_uniq_edge(G6_IRB2.loc_key, G6_IRB3.loc_key) # Expected output for graph 6 -G6_EXP_IRA = IRA.new_ircfg() +G6_EXP_cfg = Lifter.new_ircfg() G6_EXP_IRB0 = gen_irblock(LBL0, [[]]) G6_EXP_IRB1 = gen_irblock(LBL1, [[]]) @@ -249,11 +249,11 @@ G6_EXP_IRB2 = gen_irblock(LBL2, [[]]) G6_EXP_IRB3 = gen_irblock(LBL3, [[ExprAssign(r, CST2)]]) for irb in [G6_EXP_IRB0, G6_EXP_IRB1, G6_EXP_IRB2, G6_EXP_IRB3]: - G6_EXP_IRA.add_irblock(irb) + G6_EXP_cfg.add_irblock(irb) # graph 7 : Double entry loop with dead variables -G7_IRA = IRA.new_ircfg() +G7_cfg = Lifter.new_ircfg() G7_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)], [ExprAssign(r, CST1)]]) G7_IRB1 = gen_irblock(LBL1, [[ExprAssign(a, a+CST1)]]) @@ -261,17 +261,17 @@ G7_IRB2 = gen_irblock(LBL2, [[ExprAssign(a, a+CST2)]]) G7_IRB3 = gen_irblock(LBL3, [[ExprAssign(a, r)]]) for irb in [G7_IRB0, G7_IRB1, G7_IRB2, G7_IRB3]: - G7_IRA.add_irblock(irb) + G7_cfg.add_irblock(irb) -G7_IRA.add_uniq_edge(G7_IRB0.loc_key, G7_IRB1.loc_key) -G7_IRA.add_uniq_edge(G7_IRB1.loc_key, G7_IRB2.loc_key) -G7_IRA.add_uniq_edge(G7_IRB2.loc_key, G7_IRB1.loc_key) -G7_IRA.add_uniq_edge(G7_IRB2.loc_key, G7_IRB3.loc_key) -G7_IRA.add_uniq_edge(G7_IRB0.loc_key, G7_IRB2.loc_key) +G7_cfg.add_uniq_edge(G7_IRB0.loc_key, G7_IRB1.loc_key) +G7_cfg.add_uniq_edge(G7_IRB1.loc_key, G7_IRB2.loc_key) +G7_cfg.add_uniq_edge(G7_IRB2.loc_key, G7_IRB1.loc_key) +G7_cfg.add_uniq_edge(G7_IRB2.loc_key, G7_IRB3.loc_key) +G7_cfg.add_uniq_edge(G7_IRB0.loc_key, G7_IRB2.loc_key) # Expected output for graph 7 -G7_EXP_IRA = IRA.new_ircfg() +G7_EXP_cfg = Lifter.new_ircfg() G7_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAssign(r, CST1)]]) G7_EXP_IRB1 = gen_irblock(LBL1, [[]]) @@ -279,11 +279,11 @@ G7_EXP_IRB2 = gen_irblock(LBL2, [[]]) G7_EXP_IRB3 = gen_irblock(LBL3, [[]]) for irb in [G7_EXP_IRB0, G7_EXP_IRB1, G7_EXP_IRB2, G7_EXP_IRB3]: - G7_EXP_IRA.add_irblock(irb) + G7_EXP_cfg.add_irblock(irb) # graph 8 : Nested loops with dead variables -G8_IRA = IRA.new_ircfg() +G8_cfg = Lifter.new_ircfg() G8_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)], [ExprAssign(b, CST1)]]) G8_IRB1 = gen_irblock(LBL1, [[ExprAssign(a, a+CST1)]]) @@ -292,18 +292,18 @@ G8_IRB3 = gen_irblock(LBL3, [[ExprAssign(a, b)]]) for irb in [G8_IRB0, G8_IRB1, G8_IRB2, G8_IRB3]: - G8_IRA.add_irblock(irb) + G8_cfg.add_irblock(irb) -G8_IRA.add_uniq_edge(G8_IRB0.loc_key, G8_IRB1.loc_key) -G8_IRA.add_uniq_edge(G8_IRB1.loc_key, G8_IRB2.loc_key) -G8_IRA.add_uniq_edge(G8_IRB2.loc_key, G8_IRB1.loc_key) -G8_IRA.add_uniq_edge(G8_IRB2.loc_key, G8_IRB3.loc_key) -G8_IRA.add_uniq_edge(G8_IRB3.loc_key, G8_IRB2.loc_key) +G8_cfg.add_uniq_edge(G8_IRB0.loc_key, G8_IRB1.loc_key) +G8_cfg.add_uniq_edge(G8_IRB1.loc_key, G8_IRB2.loc_key) +G8_cfg.add_uniq_edge(G8_IRB2.loc_key, G8_IRB1.loc_key) +G8_cfg.add_uniq_edge(G8_IRB2.loc_key, G8_IRB3.loc_key) +G8_cfg.add_uniq_edge(G8_IRB3.loc_key, G8_IRB2.loc_key) # Expected output for graph 8 -G8_EXP_IRA = IRA.new_ircfg() +G8_EXP_cfg = Lifter.new_ircfg() G8_EXP_IRB0 = gen_irblock(LBL0, [[], []]) G8_EXP_IRB1 = gen_irblock(LBL1, [[]]) @@ -311,11 +311,11 @@ G8_EXP_IRB2 = gen_irblock(LBL2, [[]]) G8_EXP_IRB3 = gen_irblock(LBL3, [[]]) for irb in [G8_EXP_IRB0, G8_EXP_IRB1, G8_EXP_IRB2, G8_EXP_IRB3]: - G8_EXP_IRA.add_irblock(irb) + G8_EXP_cfg.add_irblock(irb) # graph 9 : Miultiple-exits loops with dead variables -G9_IRA = IRA.new_ircfg() +G9_cfg = Lifter.new_ircfg() G9_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)], [ExprAssign(b, CST1)]]) G9_IRB1 = gen_irblock(LBL1, [[ExprAssign(a, a+CST1)], [ExprAssign(b, b+CST1)]]) @@ -324,21 +324,21 @@ G9_IRB3 = gen_irblock(LBL3, [[ExprAssign(a, b)]]) G9_IRB4 = gen_irblock(LBL4, [[ExprAssign(r, a)], [ExprAssign(r, b)]]) for irb in [G9_IRB0, G9_IRB1, G9_IRB2, G9_IRB3, G9_IRB4]: - G9_IRA.add_irblock(irb) + G9_cfg.add_irblock(irb) -G9_IRA.add_uniq_edge(G9_IRB0.loc_key, G9_IRB4.loc_key) -G9_IRA.add_uniq_edge(G9_IRB0.loc_key, G9_IRB1.loc_key) -G9_IRA.add_uniq_edge(G9_IRB1.loc_key, G9_IRB0.loc_key) -G9_IRA.add_uniq_edge(G9_IRB1.loc_key, G9_IRB4.loc_key) -G9_IRA.add_uniq_edge(G9_IRB1.loc_key, G9_IRB2.loc_key) -G9_IRA.add_uniq_edge(G9_IRB2.loc_key, G9_IRB0.loc_key) -G9_IRA.add_uniq_edge(G9_IRB2.loc_key, G9_IRB3.loc_key) -G9_IRA.add_uniq_edge(G9_IRB3.loc_key, G9_IRB4.loc_key) +G9_cfg.add_uniq_edge(G9_IRB0.loc_key, G9_IRB4.loc_key) +G9_cfg.add_uniq_edge(G9_IRB0.loc_key, G9_IRB1.loc_key) +G9_cfg.add_uniq_edge(G9_IRB1.loc_key, G9_IRB0.loc_key) +G9_cfg.add_uniq_edge(G9_IRB1.loc_key, G9_IRB4.loc_key) +G9_cfg.add_uniq_edge(G9_IRB1.loc_key, G9_IRB2.loc_key) +G9_cfg.add_uniq_edge(G9_IRB2.loc_key, G9_IRB0.loc_key) +G9_cfg.add_uniq_edge(G9_IRB2.loc_key, G9_IRB3.loc_key) +G9_cfg.add_uniq_edge(G9_IRB3.loc_key, G9_IRB4.loc_key) # Expected output for graph 9 -G9_EXP_IRA = IRA.new_ircfg() +G9_EXP_cfg = Lifter.new_ircfg() G9_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAssign(b, CST1)]]) G9_EXP_IRB1 = gen_irblock(LBL1, [[], [ExprAssign(b, b+CST1)]]) @@ -347,12 +347,12 @@ G9_EXP_IRB3 = gen_irblock(LBL3, [[]]) G9_EXP_IRB4 = gen_irblock(LBL4, [[], [ExprAssign(r, b)]]) for irb in [G9_EXP_IRB0, G9_EXP_IRB1, G9_EXP_IRB2, G9_EXP_IRB3, G9_EXP_IRB4]: - G9_EXP_IRA.add_irblock(irb) + G9_EXP_cfg.add_irblock(irb) # graph 10 : Natural loop with alive variables symmetric assignment # (a = b <-> b = a ) -G10_IRA = IRA.new_ircfg() +G10_cfg = Lifter.new_ircfg() G10_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)]]) G10_IRB1 = gen_irblock(LBL1, [[ExprAssign(b, a)]]) @@ -360,16 +360,16 @@ G10_IRB2 = gen_irblock(LBL2, [[ExprAssign(a, b)]]) G10_IRB3 = gen_irblock(LBL3, [[ExprAssign(r, CST1)]]) for irb in [G10_IRB0, G10_IRB1, G10_IRB2, G10_IRB3]: - G10_IRA.add_irblock(irb) + G10_cfg.add_irblock(irb) -G10_IRA.add_uniq_edge(G10_IRB0.loc_key, G10_IRB1.loc_key) -G10_IRA.add_uniq_edge(G10_IRB1.loc_key, G10_IRB2.loc_key) -G10_IRA.add_uniq_edge(G10_IRB2.loc_key, G10_IRB1.loc_key) -G10_IRA.add_uniq_edge(G10_IRB2.loc_key, G10_IRB3.loc_key) +G10_cfg.add_uniq_edge(G10_IRB0.loc_key, G10_IRB1.loc_key) +G10_cfg.add_uniq_edge(G10_IRB1.loc_key, G10_IRB2.loc_key) +G10_cfg.add_uniq_edge(G10_IRB2.loc_key, G10_IRB1.loc_key) +G10_cfg.add_uniq_edge(G10_IRB2.loc_key, G10_IRB3.loc_key) # Expected output for graph 10 -G10_EXP_IRA = IRA.new_ircfg() +G10_EXP_cfg = Lifter.new_ircfg() G10_EXP_IRB0 = gen_irblock(LBL0, [[]]) G10_EXP_IRB1 = gen_irblock(LBL1, [[]]) @@ -377,11 +377,11 @@ G10_EXP_IRB2 = gen_irblock(LBL2, [[]]) G10_EXP_IRB3 = gen_irblock(LBL3, [[ExprAssign(r, CST1)]]) for irb in [G10_EXP_IRB0, G10_EXP_IRB1, G10_EXP_IRB2, G10_EXP_IRB3]: - G10_EXP_IRA.add_irblock(irb) + G10_EXP_cfg.add_irblock(irb) # graph 11 : If/Else conditions with alive variables -G11_IRA = IRA.new_ircfg() +G11_cfg = Lifter.new_ircfg() G11_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, b)]]) G11_IRB1 = gen_irblock(LBL1, [[ExprAssign(b, a)]]) @@ -391,17 +391,17 @@ G11_IRB4 = gen_irblock(LBL4, [[ExprAssign(b, b+CST1)]]) for irb in [G11_IRB0, G11_IRB1, G11_IRB2]: - G11_IRA.add_irblock(irb) + G11_cfg.add_irblock(irb) -G11_IRA.add_uniq_edge(G11_IRB0.loc_key, G11_IRB1.loc_key) -#G11_IRA.add_uniq_edge(G11_IRB3.loc_key, G11_IRB1.loc_key) -G11_IRA.add_uniq_edge(G11_IRB1.loc_key, G11_IRB0.loc_key) -#G11_IRA.add_uniq_edge(G11_IRB4.loc_key, G11_IRB0.loc_key) -G11_IRA.add_uniq_edge(G11_IRB1.loc_key, G11_IRB2.loc_key) +G11_cfg.add_uniq_edge(G11_IRB0.loc_key, G11_IRB1.loc_key) +#G11_cfg.add_uniq_edge(G11_IRB3.loc_key, G11_IRB1.loc_key) +G11_cfg.add_uniq_edge(G11_IRB1.loc_key, G11_IRB0.loc_key) +#G11_cfg.add_uniq_edge(G11_IRB4.loc_key, G11_IRB0.loc_key) +G11_cfg.add_uniq_edge(G11_IRB1.loc_key, G11_IRB2.loc_key) # Expected output for graph 11 -G11_EXP_IRA = IRA.new_ircfg() +G11_EXP_cfg = Lifter.new_ircfg() G11_EXP_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, b)]]) G11_EXP_IRB1 = gen_irblock(LBL1, [[ExprAssign(b, a)]]) @@ -411,12 +411,12 @@ G11_EXP_IRB2 = gen_irblock(LBL2, [[ExprAssign(r, a)]]) for irb in [G11_EXP_IRB0, G11_EXP_IRB1, G11_EXP_IRB2]: - G11_EXP_IRA.add_irblock(irb) + G11_EXP_cfg.add_irblock(irb) # graph 12 : Graph with multiple out points and useless definitions # of return register -G12_IRA = IRA.new_ircfg() +G12_cfg = Lifter.new_ircfg() G12_IRB0 = gen_irblock(LBL0, [[ExprAssign(r, CST1)], [ExprAssign(a, CST2)]]) G12_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, CST2)]]) @@ -426,16 +426,16 @@ G12_IRB4 = gen_irblock(LBL4, [[ExprAssign(r, CST2)]]) G12_IRB5 = gen_irblock(LBL5, [[ExprAssign(r, b)]]) for irb in [G12_IRB0, G12_IRB1, G12_IRB2, G12_IRB3, G12_IRB4, G12_IRB5]: - G12_IRA.add_irblock(irb) + G12_cfg.add_irblock(irb) -G12_IRA.add_uniq_edge(G12_IRB0.loc_key, G12_IRB1.loc_key) -G12_IRA.add_uniq_edge(G12_IRB0.loc_key, G12_IRB2.loc_key) -G12_IRA.add_uniq_edge(G12_IRB2.loc_key, G12_IRB3.loc_key) -G12_IRA.add_uniq_edge(G12_IRB2.loc_key, G12_IRB4.loc_key) -G12_IRA.add_uniq_edge(G12_IRB4.loc_key, G12_IRB5.loc_key) +G12_cfg.add_uniq_edge(G12_IRB0.loc_key, G12_IRB1.loc_key) +G12_cfg.add_uniq_edge(G12_IRB0.loc_key, G12_IRB2.loc_key) +G12_cfg.add_uniq_edge(G12_IRB2.loc_key, G12_IRB3.loc_key) +G12_cfg.add_uniq_edge(G12_IRB2.loc_key, G12_IRB4.loc_key) +G12_cfg.add_uniq_edge(G12_IRB4.loc_key, G12_IRB5.loc_key) # Expected output for graph 12 -G12_EXP_IRA = IRA.new_ircfg() +G12_EXP_cfg = Lifter.new_ircfg() G12_EXP_IRB0 = gen_irblock(LBL0, [[], []]) G12_EXP_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, CST2)]]) @@ -448,11 +448,11 @@ G12_EXP_IRB5 = gen_irblock(LBL5, [[ExprAssign(r, b)]]) for irb in [G12_EXP_IRB0, G12_EXP_IRB1, G12_EXP_IRB2, G12_EXP_IRB3, G12_EXP_IRB4, G12_EXP_IRB5]: - G12_EXP_IRA.add_irblock(irb) + G12_EXP_cfg.add_irblock(irb) # graph 13 : Graph where a leaf has lost its son -G13_IRA = IRA.new_ircfg() +G13_cfg = Lifter.new_ircfg() G13_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)], [ExprAssign(b, CST2)]]) G13_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, b)]]) @@ -462,15 +462,15 @@ G13_IRB3 = gen_irblock(LBL3, [[]]) # lost son G13_IRB4 = gen_irblock(LBL4, [[ExprAssign(b, CST2)]]) for irb in [G13_IRB0, G13_IRB1, G13_IRB2, G13_IRB4]: - G13_IRA.add_irblock(irb) + G13_cfg.add_irblock(irb) -G13_IRA.add_uniq_edge(G13_IRB0.loc_key, G13_IRB1.loc_key) -G13_IRA.add_uniq_edge(G13_IRB0.loc_key, G13_IRB4.loc_key) -G13_IRA.add_uniq_edge(G13_IRB2.loc_key, G13_IRB3.loc_key) -G13_IRA.add_uniq_edge(G13_IRB4.loc_key, G13_IRB2.loc_key) +G13_cfg.add_uniq_edge(G13_IRB0.loc_key, G13_IRB1.loc_key) +G13_cfg.add_uniq_edge(G13_IRB0.loc_key, G13_IRB4.loc_key) +G13_cfg.add_uniq_edge(G13_IRB2.loc_key, G13_IRB3.loc_key) +G13_cfg.add_uniq_edge(G13_IRB4.loc_key, G13_IRB2.loc_key) # Expected output for graph 13 -G13_EXP_IRA = IRA.new_ircfg() +G13_EXP_cfg = Lifter.new_ircfg() G13_EXP_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)], [ExprAssign(b, CST2)]]) G13_EXP_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, b)]]) @@ -480,38 +480,38 @@ G13_EXP_IRB3 = gen_irblock(LBL3, [[]]) G13_EXP_IRB4 = gen_irblock(LBL4, [[ExprAssign(b, CST2)]]) for irb in [G13_EXP_IRB0, G13_EXP_IRB1, G13_EXP_IRB2, G13_EXP_IRB4]: - G13_EXP_IRA.add_irblock(irb) + G13_EXP_cfg.add_irblock(irb) -#G13_EXP_IRA = G13_IRA +#G13_EXP_cfg = G13_cfg # graph 14 : Graph where variable assigned multiple times in a block but still # useful in the end -G14_IRA = IRA.new_ircfg() +G14_cfg = Lifter.new_ircfg() G14_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)], [ExprAssign(c, a)], [ExprAssign(a, CST2)]]) G14_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, a+c)]]) for irb in [G14_IRB0, G14_IRB1]: - G14_IRA.add_irblock(irb) + G14_cfg.add_irblock(irb) -G14_IRA.add_uniq_edge(G14_IRB0.loc_key, G14_IRB1.loc_key) +G14_cfg.add_uniq_edge(G14_IRB0.loc_key, G14_IRB1.loc_key) # Expected output for graph 1 -G14_EXP_IRA = IRA.new_ircfg() +G14_EXP_cfg = Lifter.new_ircfg() G14_EXP_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1)], [ExprAssign(c, a)], [ExprAssign(a, CST2)]]) G14_EXP_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, a+c)]]) for irb in [G14_EXP_IRB0, G14_EXP_IRB1]: - G14_EXP_IRA.add_irblock(irb) + G14_EXP_cfg.add_irblock(irb) # graph 15 : Graph where variable assigned multiple and read at the same time, # but useless -G15_IRA = IRA.new_ircfg() +G15_cfg = Lifter.new_ircfg() G15_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST2)], [ExprAssign(a, CST1), ExprAssign(b, a+CST2), @@ -519,22 +519,22 @@ G15_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST2)], [ExprAssign(a, CST1), G15_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, a)]]) for irb in [G15_IRB0, G15_IRB1]: - G15_IRA.add_irblock(irb) + G15_cfg.add_irblock(irb) -G15_IRA.add_uniq_edge(G15_IRB0.loc_key, G15_IRB1.loc_key) +G15_cfg.add_uniq_edge(G15_IRB0.loc_key, G15_IRB1.loc_key) # Expected output for graph 1 -G15_EXP_IRA = IRA.new_ircfg() +G15_EXP_cfg = Lifter.new_ircfg() G15_EXP_IRB0 = gen_irblock(LBL0, [[], [ExprAssign(a, CST1)]]) G15_EXP_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, a)]]) for irb in [G15_EXP_IRB0, G15_EXP_IRB1]: - G15_EXP_IRA.add_irblock(irb) + G15_EXP_cfg.add_irblock(irb) # graph 16 : Graph where variable assigned multiple times in the same block -G16_IRA = IRA.new_ircfg() +G16_cfg = Lifter.new_ircfg() G16_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, CST1), ExprAssign(b, CST2), ExprAssign(c, CST3)], [ExprAssign(a, c+CST1), @@ -543,27 +543,27 @@ G16_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, a+b)], [ExprAssign(r, c+r)]]) G16_IRB2 = gen_irblock(LBL2, [[]]) for irb in [G16_IRB0, G16_IRB1]: - G16_IRA.add_irblock(irb) + G16_cfg.add_irblock(irb) -G16_IRA.add_uniq_edge(G16_IRB0.loc_key, G16_IRB1.loc_key) -G16_IRA.add_uniq_edge(G16_IRB1.loc_key, G16_IRB2.loc_key) +G16_cfg.add_uniq_edge(G16_IRB0.loc_key, G16_IRB1.loc_key) +G16_cfg.add_uniq_edge(G16_IRB1.loc_key, G16_IRB2.loc_key) for irb in [G16_IRB0, G16_IRB1]: - G16_IRA.add_irblock(irb) + G16_cfg.add_irblock(irb) # Expected output for graph 1 -G16_EXP_IRA = IRA.new_ircfg() +G16_EXP_cfg = Lifter.new_ircfg() G16_EXP_IRB0 = gen_irblock(LBL0, [[ExprAssign(c, CST3)], [ExprAssign(a, c + CST1), ExprAssign(b, c + CST2)]]) G16_EXP_IRB1 = gen_irblock(LBL1, [[ExprAssign(r, a+b)], [ExprAssign(r, c+r)]]) for irb in [G16_EXP_IRB0, G16_EXP_IRB1]: - G16_EXP_IRA.add_irblock(irb) + G16_EXP_cfg.add_irblock(irb) # graph 17 : parallel ir -G17_IRA = IRA.new_ircfg() +G17_cfg = Lifter.new_ircfg() G17_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, a*b), ExprAssign(b, c), @@ -620,12 +620,12 @@ G17_IRB0 = gen_irblock(LBL0, [[ExprAssign(a, a*b), ]) for irb in [G17_IRB0]: - G17_IRA.add_irblock(irb) + G17_cfg.add_irblock(irb) -#G17_IRA.graph.add_node(G17_IRB0.loc_key) +#G17_cfg.graph.add_node(G17_IRB0.loc_key) # Expected output for graph 17 -G17_EXP_IRA = IRA.new_ircfg() +G17_EXP_cfg = Lifter.new_ircfg() G17_EXP_IRB0 = gen_irblock(LBL0, [[], @@ -663,48 +663,48 @@ G17_EXP_IRB0 = gen_irblock(LBL0, [[], ]) for irb in [G17_EXP_IRB0]: - G17_EXP_IRA.add_irblock(irb) + G17_EXP_cfg.add_irblock(irb) # Beginning of tests -for test_nb, test in enumerate([(G1_IRA, G1_EXP_IRA), - (G2_IRA, G2_EXP_IRA), - (G3_IRA, G3_EXP_IRA), - (G4_IRA, G4_EXP_IRA), - (G5_IRA, G5_EXP_IRA), - (G6_IRA, G6_EXP_IRA), - (G7_IRA, G7_EXP_IRA), - (G8_IRA, G8_EXP_IRA), - (G9_IRA, G9_EXP_IRA), - (G10_IRA, G10_EXP_IRA), - (G11_IRA, G11_EXP_IRA), - (G12_IRA, G12_EXP_IRA), - (G13_IRA, G13_EXP_IRA), - (G14_IRA, G14_EXP_IRA), - (G15_IRA, G15_EXP_IRA), - (G16_IRA, G16_EXP_IRA), - (G17_IRA, G17_EXP_IRA) +for test_nb, test in enumerate([(G1_cfg, G1_EXP_cfg), + (G2_cfg, G2_EXP_cfg), + (G3_cfg, G3_EXP_cfg), + (G4_cfg, G4_EXP_cfg), + (G5_cfg, G5_EXP_cfg), + (G6_cfg, G6_EXP_cfg), + (G7_cfg, G7_EXP_cfg), + (G8_cfg, G8_EXP_cfg), + (G9_cfg, G9_EXP_cfg), + (G10_cfg, G10_EXP_cfg), + (G11_cfg, G11_EXP_cfg), + (G12_cfg, G12_EXP_cfg), + (G13_cfg, G13_EXP_cfg), + (G14_cfg, G14_EXP_cfg), + (G15_cfg, G15_EXP_cfg), + (G16_cfg, G16_EXP_cfg), + (G17_cfg, G17_EXP_cfg) ]): # Extract test elements - g_ira, g_exp_ira = test + g_ircfg, g_exp_ircfg = test print("[+] Test", test_nb+1) # Print initial graph, for debug - open("graph_%02d.dot" % (test_nb+1), "w").write(g_ira.dot()) + open("graph_%02d.dot" % (test_nb+1), "w").write(g_ircfg.dot()) - reaching_defs = ReachingDefinitions(g_ira) + reaching_defs = ReachingDefinitions(g_ircfg) defuse = DiGraphDefUse(reaching_defs, deref_mem=True) # # Simplify graph - deadrm(g_ira) + deadrm(g_ircfg) # # Print simplified graph, for debug - open("simp_graph_%02d.dot" % (test_nb+1), "w").write(g_ira.dot()) + open("simp_graph_%02d.dot" % (test_nb+1), "w").write(g_ircfg.dot()) # Same number of blocks - assert len(g_ira.blocks) == len(g_exp_ira.blocks) + assert len(g_ircfg.blocks) == len(g_exp_ircfg.blocks) # Check that each expr in the blocks are the same - for lbl, irb in viewitems(g_ira.blocks): - exp_irb = g_exp_ira.blocks[lbl] + for lbl, irb in viewitems(g_ircfg.blocks): + exp_irb = g_exp_ircfg.blocks[lbl] assert exp_irb.assignblks == irb.assignblks diff --git a/test/analysis/depgraph.py b/test/analysis/depgraph.py index 49a395a1..f0b67737 100644 --- a/test/analysis/depgraph.py +++ b/test/analysis/depgraph.py @@ -6,7 +6,7 @@ from future.utils import viewitems from miasm.expression.expression import ExprId, ExprInt, ExprAssign, \ ExprCond, ExprLoc, LocKey from miasm.core.locationdb import LocationDB -from miasm.ir.analysis import ira +from miasm.ir.analysis import LifterModelCall from miasm.ir.ir import IRBlock, AssignBlock from miasm.core.graph import DiGraph from miasm.analysis.depgraph import DependencyNode, DependencyGraph @@ -91,7 +91,7 @@ class Arch(object): return SP -class IRATest(ira): +class IRATest(LifterModelCall): """Fake IRA class for tests""" diff --git a/test/analysis/dse.py b/test/analysis/dse.py index 570860e4..7a2843e0 100644 --- a/test/analysis/dse.py +++ b/test/analysis/dse.py @@ -90,7 +90,7 @@ class DSETest(object): self.assembly = bytes(output) def check(self): - regs = self.dse.ir_arch.arch.regs + regs = self.dse.lifter.arch.regs value = self.dse.eval_expr(regs.EDX) # The expected value should contains '<<', showing it has been in the # corresponding generated label @@ -116,8 +116,8 @@ class DSEAttachInBreakpoint(DSETest): def __init__(self, *args, **kwargs): super(DSEAttachInBreakpoint, self).__init__(*args, **kwargs) self._dse = None - ircls = self.machine.ir - self._regs = ircls(self.loc_db).arch.regs + lifter_cls = self.machine.lifter + self._regs = lifter_cls(self.loc_db).arch.regs self._testid = ExprId("TEST", self._regs.EBX.size) def bp_attach(self, jitter): diff --git a/test/analysis/unssa.py b/test/analysis/unssa.py index 5844bfb4..bc7db487 100644 --- a/test/analysis/unssa.py +++ b/test/analysis/unssa.py @@ -5,7 +5,7 @@ from miasm.expression.expression import ExprId, ExprInt, ExprAssign, ExprMem, \ ExprCond, ExprLoc from miasm.core.locationdb import LocationDB from miasm.analysis.simplifier import IRCFGSimplifierSSA -from miasm.ir.analysis import ira +from miasm.ir.analysis import LifterModelCall from miasm.ir.ir import IRCFG, IRBlock, AssignBlock loc_db = LocationDB() @@ -73,7 +73,7 @@ class Arch(object): def getsp(self, _): return sp -class IRATest(ira): +class IRATest(LifterModelCall): """Fake IRA class for tests""" @@ -601,8 +601,8 @@ class CustomIRCFGSimplifierSSA(IRCFGSimplifierSSA): """ regs = set( [ - self.ir_arch.pc, - self.ir_arch.IRDst, + self.lifter.pc, + self.lifter.IRDst, ] ) return regs diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py index 49d46a4d..1dca9a6b 100755 --- a/test/arch/arm/sem.py +++ b/test/arch/arm/sem.py @@ -9,7 +9,7 @@ from future.utils import viewitems from miasm.ir.symbexec import SymbolicExecutionEngine from miasm.arch.arm.arch import mn_arm as mn -from miasm.arch.arm.sem import ir_arml as ir_arch +from miasm.arch.arm.sem import Lifter_Arml as ir_arch from miasm.arch.arm.regs import * from miasm.expression.expression import * from miasm.core.locationdb import LocationDB diff --git a/test/arch/mep/ir/test_ir.py b/test/arch/mep/ir/test_ir.py index 97a3ec1e..87389e30 100644 --- a/test/arch/mep/ir/test_ir.py +++ b/test/arch/mep/ir/test_ir.py @@ -6,7 +6,7 @@ from __future__ import print_function from miasm.core.utils import decode_hex from miasm.arch.mep.arch import mn_mep from miasm.arch.mep.regs import regs_init -from miasm.arch.mep.ira import ir_mepb, ir_a_mepb +from miasm.arch.mep.lifter_model_call import Lifter_MEPb, LifterModelCallMepb from miasm.expression.expression import ExprId, ExprInt, ExprMem from miasm.ir.symbexec import SymbolicExecutionEngine from miasm.core.locationdb import LocationDB @@ -30,12 +30,12 @@ class TestMisc(object): loc_db = LocationDB() # Get the IR - im = ir_mepb(loc_db) + im = Lifter_MEPb(loc_db) iir, eiir, = im.get_ir(mn) print("\nInternal representation:", iir) # Symbolic execution - sb = SymbolicExecutionEngine(ir_a_mepb(loc_db), regs_init) + sb = SymbolicExecutionEngine(LifterModelCallMepb(loc_db), regs_init) # Assign register values before symbolic evaluation for reg_expr_id, reg_expr_value in init_values: diff --git a/test/arch/mep/ir/ut_helpers_ir.py b/test/arch/mep/ir/ut_helpers_ir.py index c5bf36b9..e4b2df43 100644 --- a/test/arch/mep/ir/ut_helpers_ir.py +++ b/test/arch/mep/ir/ut_helpers_ir.py @@ -4,14 +4,14 @@ from __future__ import print_function from miasm.arch.mep.arch import mn_mep -from miasm.arch.mep.sem import ir_mepb +from miasm.arch.mep.sem import Lifter_MEPb from miasm.arch.mep.regs import regs_init from miasm.ir.symbexec import SymbolicExecutionEngine from miasm.core.locationdb import LocationDB from miasm.core.utils import Disasm_Exception from miasm.ir.ir import AssignBlock -from miasm.arch.mep.ira import ir_a_mepb +from miasm.arch.mep.lifter_model_call import LifterModelCallMepb from miasm.expression.expression import ExprId, ExprInt, ExprOp, ExprMem, \ ExprAssign, ExprLoc @@ -35,7 +35,7 @@ def exec_instruction(mn_str, init_values, results, index=0, offset=0): instr.dstflow2label(loc_db) # Get the IR - im = ir_mepb(loc_db) + im = Lifter_MEPb(loc_db) iir, eiir = im.get_ir(instr) # Filter out IRDst @@ -44,7 +44,7 @@ def exec_instruction(mn_str, init_values, results, index=0, offset=0): ir.dst.name == "IRDst")] # Prepare symbolic execution - sb = SymbolicExecutionEngine(ir_a_mepb(loc_db), regs_init) + sb = SymbolicExecutionEngine(LifterModelCallMepb(loc_db), regs_init) # Assign int values before symbolic evaluation for expr_id, expr_value in init_values: diff --git a/test/arch/msp430/sem.py b/test/arch/msp430/sem.py index 2b3c4afe..e47c6f30 100755 --- a/test/arch/msp430/sem.py +++ b/test/arch/msp430/sem.py @@ -9,7 +9,7 @@ from future.utils import viewitems from miasm.ir.symbexec import SymbolicExecutionEngine from miasm.arch.msp430.arch import mn_msp430 as mn, mode_msp430 as mode -from miasm.arch.msp430.sem import ir_msp430 as ir_arch +from miasm.arch.msp430.sem import Lifter_MSP430 as ir_arch from miasm.arch.msp430.regs import * from miasm.expression.expression import * from miasm.core.locationdb import LocationDB diff --git a/test/arch/ppc32/sem.py b/test/arch/ppc32/sem.py index 53c93369..c4b08485 100644 --- a/test/arch/ppc32/sem.py +++ b/test/arch/ppc32/sem.py @@ -9,7 +9,7 @@ from future.utils import viewitems from miasm.ir.symbexec import SymbolicExecutionEngine from miasm.arch.ppc.arch import mn_ppc as mn -from miasm.arch.ppc.sem import ir_ppc32b as ir_arch +from miasm.arch.ppc.sem import Lifter_PPC32b as ir_arch from miasm.arch.ppc.regs import * from miasm.expression.expression import * from miasm.core.locationdb import LocationDB diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 0455462d..bedbc503 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -6,7 +6,7 @@ from miasm.core.utils import decode_hex, encode_hex import miasm.expression.expression as m2_expr from miasm.arch.x86.arch import mn_x86, deref_mem_ad, \ base_expr, rmarg, print_size -from miasm.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 +from miasm.arch.x86.sem import Lifter_X86_16, Lifter_X86_32, Lifter_X86_64 from miasm.core.bin_stream import bin_stream_str from miasm.core.locationdb import LocationDB diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py index 9c7e972b..ecee5772 100755 --- a/test/arch/x86/sem.py +++ b/test/arch/x86/sem.py @@ -14,7 +14,7 @@ import copy from miasm.ir.symbexec import SymbolicExecutionEngine from miasm.arch.x86.arch import mn_x86 as mn -from miasm.arch.x86.sem import ir_x86_32 as ir_32, ir_x86_64 as ir_64 +from miasm.arch.x86.sem import Lifter_X86_32 as ir_32, Lifter_X86_64 as ir_64 from miasm.arch.x86.regs import * from miasm.expression.expression import * from miasm.expression.simplifications import expr_simp diff --git a/test/ir/reduce_graph.py b/test/ir/reduce_graph.py index 4aa2d5ef..5142cf5a 100644 --- a/test/ir/reduce_graph.py +++ b/test/ir/reduce_graph.py @@ -9,7 +9,7 @@ from miasm.expression.expression import ExprId, ExprInt, ExprAssign, ExprCond, \ ExprLoc, LocKey from miasm.core.locationdb import LocationDB -from miasm.ir.analysis import ira +from miasm.ir.analysis import LifterModelCall from miasm.ir.ir import IRBlock, AssignBlock, IRCFG from miasm.analysis.data_flow import merge_blocks @@ -70,7 +70,7 @@ class Arch(object): return SP -class IRATest(ira): +class IRATest(LifterModelCall): """Fake IRA class for tests""" diff --git a/test/ir/symbexec.py b/test/ir/symbexec.py index d627f4b9..0ab7e5a7 100755 --- a/test/ir/symbexec.py +++ b/test/ir/symbexec.py @@ -13,15 +13,15 @@ class TestSymbExec(unittest.TestCase): def test_ClassDef(self): from miasm.expression.expression import ExprInt, ExprId, ExprMem, \ ExprCompose, ExprAssign - from miasm.arch.x86.sem import ir_x86_32 + from miasm.arch.x86.sem import Lifter_X86_32 from miasm.core.locationdb import LocationDB from miasm.ir.symbexec import SymbolicExecutionEngine from miasm.ir.ir import AssignBlock loc_db = LocationDB() - ira = ir_x86_32(loc_db) - ircfg = ira.new_ircfg() + lifter_model_call = Lifter_X86_32(loc_db) + ircfg = lifter_model_call.new_ircfg() id_x = ExprId('x', 32) id_a = ExprId('a', 32) @@ -36,7 +36,7 @@ class TestSymbExec(unittest.TestCase): return id_x return super(CustomSymbExec, self).mem_read(expr) - sb = CustomSymbExec(ira, + sb = CustomSymbExec(lifter_model_call, { ExprMem(ExprInt(0x4, 32), 8): ExprInt(0x44, 8), ExprMem(ExprInt(0x5, 32), 8): ExprInt(0x33, 8), @@ -229,13 +229,13 @@ class TestSymbExec(unittest.TestCase): assert found - sb_empty = SymbolicExecutionEngine(ira) + sb_empty = SymbolicExecutionEngine(lifter_model_call) sb_empty.dump() # Test memory full print('full') - arch_addr8 = ir_x86_32(loc_db) + arch_addr8 = Lifter_X86_32(loc_db) ircfg = arch_addr8.new_ircfg() # Hack to obtain tiny address space arch_addr8.addrsize = 5 diff --git a/test/test_all.py b/test/test_all.py index c2391572..f0ac755e 100755 --- a/test/test_all.py +++ b/test/test_all.py @@ -600,10 +600,10 @@ for script, prods, depends in [ (["dis_x86_string.py"], ["str_cfg.dot"], []), (["dis_binary.py", Example.get_sample("test_x86_32_dis.bin"), ], ["bin_cfg.dot"], [test_x86_32_dis]), - (["dis_binary_ir.py", Example.get_sample("test_x86_32_dis.bin"), + (["dis_binary_lift.py", Example.get_sample("test_x86_32_dis.bin"), ], ["bin_ir_cfg.dot"], [test_x86_32_dis]), - (["dis_binary_ira.py", Example.get_sample("test_x86_32_dis.bin"), - ], ["bin_ira_cfg.dot"], [test_x86_32_dis]), + (["dis_binary_lift_model_call.py", Example.get_sample("test_x86_32_dis.bin"), + ], ["bin_lifter_model_call_cfg.dot"], [test_x86_32_dis]), (["full.py", Example.get_sample("box_upx.exe")], ["graph_execflow.dot", "lines.dot"], []), ]: |