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-rw-r--r--example/disasm/full.py2
-rw-r--r--example/ida/depgraph.py2
-rw-r--r--miasm2/analysis/data_flow.py2
-rw-r--r--miasm2/analysis/depgraph.py2
-rw-r--r--miasm2/arch/x86/arch.py2
-rw-r--r--miasm2/arch/x86/sem.py8
-rw-r--r--miasm2/core/types.py2
-rw-r--r--miasm2/expression/expression.py6
-rw-r--r--miasm2/ir/ir.py2
-rw-r--r--miasm2/ir/symbexec.py2
-rw-r--r--miasm2/ir/symbexec_types.py2
-rw-r--r--miasm2/jitter/codegen.py2
-rw-r--r--miasm2/jitter/llvmconvert.py36
-rw-r--r--test/analysis/data_flow.py4
14 files changed, 37 insertions, 37 deletions
diff --git a/example/disasm/full.py b/example/disasm/full.py
index 153666f2..cc7f9be8 100644
--- a/example/disasm/full.py
+++ b/example/disasm/full.py
@@ -305,7 +305,7 @@ if args.propagexpr:
                         out[reg] = dst
             return set(out.values())
 
-    # Add dummy dependency to uncover out regs affectation
+    # Add dummy dependency to uncover out regs assignment
     for loc in ircfg_a.leaves():
         irblock = ircfg_a.blocks.get(loc)
         if irblock is None:
diff --git a/example/ida/depgraph.py b/example/ida/depgraph.py
index 13c37eee..2c79c05d 100644
--- a/example/ida/depgraph.py
+++ b/example/ida/depgraph.py
@@ -227,7 +227,7 @@ def launch_depgraph():
     settings.Execute()
 
     loc_key, elements, line_nb = settings.loc_key, settings.elements, settings.line_nb
-    # Simplify affectations
+    # Simplify assignments
     for irb in ircfg.blocks.values():
         irs = []
         offset = ir_arch.loc_db.get_location_offset(irb.loc_key)
diff --git a/miasm2/analysis/data_flow.py b/miasm2/analysis/data_flow.py
index b90bdaf9..799b17d0 100644
--- a/miasm2/analysis/data_flow.py
+++ b/miasm2/analysis/data_flow.py
@@ -243,7 +243,7 @@ def dead_simp_useful_assignblks(irarch, defuse, reaching_defs):
 
 def dead_simp(irarch, ircfg):
     """
-    Remove useless affectations.
+    Remove useless assignments.
 
     This function is used to analyse relation of a * complete function *
     This means the blocks under study represent a solid full function graph.
diff --git a/miasm2/analysis/depgraph.py b/miasm2/analysis/depgraph.py
index 62967991..4e5f0433 100644
--- a/miasm2/analysis/depgraph.py
+++ b/miasm2/analysis/depgraph.py
@@ -290,7 +290,7 @@ class DependencyResult(DependencyState):
             ctx_init.update(ctx)
         assignblks = []
 
-        # Build a single affectation block according to history
+        # Build a single assignment block according to history
         last_index = len(self.relevant_loc_keys)
         for index, loc_key in enumerate(reversed(self.relevant_loc_keys), 1):
             if index == last_index and loc_key == self.initial_state.loc_key:
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index 11c1e00f..7f9d50e6 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -902,7 +902,7 @@ class mn_x86(cls_mn):
             if hasattr(c, "fadmode") and v_admode(c) != c.fadmode.mode:
                 continue
             # relative dstflow must not have opmode set
-            # (affect IP instead of EIP for instance)
+            # (assign IP instead of EIP for instance)
             if (instr.dstflow() and
                 instr.name not in ["JCXZ", "JECXZ", "JRCXZ"] and
                 len(instr.args) == 1 and
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index e01adcbc..862240e5 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -1710,7 +1710,7 @@ def div(ir, instr, src1):
     c_d = m2_expr.ExprOp('udiv', src2, src1.zeroExtend(src2.size))
     c_r = m2_expr.ExprOp('umod', src2, src1.zeroExtend(src2.size))
 
-    # if 8 bit div, only ax is affected
+    # if 8 bit div, only ax is assigned
     if size == 8:
         e.append(m2_expr.ExprAssign(src2, m2_expr.ExprCompose(c_d[:8], c_r[:8])))
     else:
@@ -1757,7 +1757,7 @@ def idiv(ir, instr, src1):
     c_d = m2_expr.ExprOp('sdiv', src2, src1.signExtend(src2.size))
     c_r = m2_expr.ExprOp('smod', src2, src1.signExtend(src2.size))
 
-    # if 8 bit div, only ax is affected
+    # if 8 bit div, only ax is assigned
     if size == 8:
         e.append(m2_expr.ExprAssign(src2, m2_expr.ExprCompose(c_d[:8], c_r[:8])))
     else:
@@ -4026,7 +4026,7 @@ cmpordsd = vec_op_clip('ord', 64, lambda x: _float_compare_to_mask(x))
 def pand(_, instr, dst, src):
     e = []
     result = dst & src
-    # No flag affected
+    # No flag assigned
     e.append(m2_expr.ExprAssign(dst, result))
     return e, []
 
@@ -4034,7 +4034,7 @@ def pand(_, instr, dst, src):
 def pandn(_, instr, dst, src):
     e = []
     result = (dst ^ dst.mask) & src
-    # No flag affected
+    # No flag assigned
     e.append(m2_expr.ExprAssign(dst, result))
     return e, []
 
diff --git a/miasm2/core/types.py b/miasm2/core/types.py
index 5d9a8d27..051c4cca 100644
--- a/miasm2/core/types.py
+++ b/miasm2/core/types.py
@@ -886,7 +886,7 @@ class Bits(Type):
     bits of a Num.
 
     The @backing_num is used to know how to serialize/deserialize data in vm,
-    but getting/setting this fields only affects bits from @bit_offset to
+    but getting/setting this fields only assign bits from @bit_offset to
     @bit_offset + @bits. Masking and shifting is handled by the class, the aim
     is to provide a transparent way to set and get some bits of a num.
     """
diff --git a/miasm2/expression/expression.py b/miasm2/expression/expression.py
index e7657860..925190ca 100644
--- a/miasm2/expression/expression.py
+++ b/miasm2/expression/expression.py
@@ -669,7 +669,7 @@ class ExprLoc(Expr):
 
 class ExprAssign(Expr):
 
-    """An ExprAssign represent an affection from an Expression to another one.
+    """An ExprAssign represent an assignment from an Expression to another one.
 
     Some use cases:
      - var1 <- 2
@@ -679,8 +679,8 @@ class ExprAssign(Expr):
 
     def __init__(self, dst, src):
         """Create an ExprAssign for dst <- src
-        @dst: Expr, affectation destination
-        @src: Expr, affectation source
+        @dst: Expr, assignment destination
+        @src: Expr, assignment source
         """
         # dst & src must be Expr
         assert isinstance(dst, Expr)
diff --git a/miasm2/ir/ir.py b/miasm2/ir/ir.py
index 72f775fb..dc1d203b 100644
--- a/miasm2/ir/ir.py
+++ b/miasm2/ir/ir.py
@@ -84,7 +84,7 @@ class AssignBlock(object):
     def _set(self, dst, src):
         """
         Special cases:
-        * if dst is an ExprSlice, expand it to affect the full Expression
+        * if dst is an ExprSlice, expand it to assign the full Expression
         * if dst already known, sources are merged
         """
         if dst.size != src.size:
diff --git a/miasm2/ir/symbexec.py b/miasm2/ir/symbexec.py
index a1ffebf5..1347e0e5 100644
--- a/miasm2/ir/symbexec.py
+++ b/miasm2/ir/symbexec.py
@@ -119,7 +119,7 @@ class MemArray(MutableMapping):
 
     The value associated to a given offset is a description of the slice of a
     stored expression. The slice size depends on the configutation of the
-    MemArray. For example, for a slice size of 8 bits, the affectation:
+    MemArray. For example, for a slice size of 8 bits, the assignment:
     - @32[EAX+0x10] = EBX
 
     will store for the base EAX:
diff --git a/miasm2/ir/symbexec_types.py b/miasm2/ir/symbexec_types.py
index 7580d1f8..71e5d6fa 100644
--- a/miasm2/ir/symbexec_types.py
+++ b/miasm2/ir/symbexec_types.py
@@ -95,7 +95,7 @@ class SymbExecCType(SymbolicExecutionEngine):
             elif isinstance(dst, ExprId):
                 pool_out[dst] = frozenset(objcs)
             else:
-                raise ValueError("Unsupported affectation", str(dst))
+                raise ValueError("Unsupported assignment", str(dst))
         return pool_out
 
     def eval_expr(self, expr, eval_cache=None):
diff --git a/miasm2/jitter/codegen.py b/miasm2/jitter/codegen.py
index a9405472..65df0c03 100644
--- a/miasm2/jitter/codegen.py
+++ b/miasm2/jitter/codegen.py
@@ -256,7 +256,7 @@ class CGen(object):
             elif isinstance(dst, ExprId):
                 new_dst = self.add_local_var(dst_var, dst_index, dst)
                 if dst in self.ir_arch.arch.regs.regs_flt_expr:
-                    # Don't mask float affectation
+                    # Don't mask float assignment
                     c_main.append(
                         '%s = (%s);' % (self.id_to_c(new_dst), self.id_to_c(src)))
                 elif new_dst.size <= self.translator.NATIVE_INT_MAX_SIZE:
diff --git a/miasm2/jitter/llvmconvert.py b/miasm2/jitter/llvmconvert.py
index 41461c3a..a31348cf 100644
--- a/miasm2/jitter/llvmconvert.py
+++ b/miasm2/jitter/llvmconvert.py
@@ -668,8 +668,8 @@ class LLVMFunction(object):
 
     # Effective constructors
 
-    def affect(self, src, dst):
-        "Affect from LLVM src to M2 dst"
+    def assign(self, src, dst):
+        "Assign from LLVM src to M2 dst"
 
         # Destination
         builder = self.builder
@@ -682,7 +682,7 @@ class LLVMFunction(object):
             addr = self.add_ir(dst.ptr)
             self.llvm_context.memory_write(self, addr, dst.size, src)
         else:
-            raise Exception("UnknownAffectationType")
+            raise Exception("UnknownAssignmentType")
 
     def init_fc(self):
         "Init the function"
@@ -1231,8 +1231,8 @@ class LLVMFunction(object):
         PC = self.llvm_context.PC
         if isinstance(offset, (int, long)):
             offset = self.add_ir(ExprInt(offset, PC.size))
-        self.affect(offset, PC)
-        self.affect(self.add_ir(ExprInt(1, 8)), ExprId("status", 32))
+        self.assign(offset, PC)
+        self.assign(self.add_ir(ExprInt(1, 8)), ExprId("status", 32))
         self.set_ret(offset)
 
         builder.position_at_end(merge_block)
@@ -1278,8 +1278,8 @@ class LLVMFunction(object):
         PC = self.llvm_context.PC
         if isinstance(offset, (int, long)):
             offset = self.add_ir(ExprInt(offset, PC.size))
-        self.affect(offset, PC)
-        self.affect(self.add_ir(ExprInt(1, 8)), ExprId("status", 32))
+        self.assign(offset, PC)
+        self.assign(self.add_ir(ExprInt(1, 8)), ExprId("status", 32))
         self.set_ret(offset)
 
         builder.position_at_end(merge_block)
@@ -1298,7 +1298,7 @@ class LLVMFunction(object):
             PC = self.llvm_context.PC
             t_size = LLVMType.IntType(PC.size)
             dst = self.builder.zext(t_size(pc_value), t_size)
-            self.affect(dst, PC)
+            self.assign(dst, PC)
 
             fc_ptr = self.mod.get_global(self.llvm_context.logging_func)
             self.builder.call(fc_ptr, [self.local_vars["vmcpu"]])
@@ -1398,9 +1398,9 @@ class LLVMFunction(object):
             dst = self.builder.zext(dst, LLVMType.IntType(PC.size))
 
         self.gen_post_code(attrib, offset)
-        self.affect(dst, PC)
+        self.assign(dst, PC)
         self.gen_post_instr_checks(attrib, dst)
-        self.affect(self.add_ir(ExprInt(0, 8)), ExprId("status", 32))
+        self.assign(self.add_ir(ExprInt(0, 8)), ExprId("status", 32))
         self.set_ret(dst)
 
 
@@ -1443,7 +1443,7 @@ class LLVMFunction(object):
             # Update the memory
             for dst, src in values.iteritems():
                 if isinstance(dst, ExprMem):
-                    self.affect(src, dst)
+                    self.assign(src, dst)
 
             # Check memory write exception
             if attributes[index].mem_write:
@@ -1453,7 +1453,7 @@ class LLVMFunction(object):
             # Update registers values
             for dst, src in values.iteritems():
                 if not isinstance(dst, ExprMem):
-                    self.affect(src, dst)
+                    self.assign(src, dst)
 
             # Check post assignblk exception flags
             if attributes[index].set_exception:
@@ -1493,9 +1493,9 @@ class LLVMFunction(object):
         builder = self.builder
         m2_exception_flag = self.llvm_context.ir_arch.arch.regs.exception_flags
         t_size = LLVMType.IntType(m2_exception_flag.size)
-        self.affect(self.add_ir(ExprInt(1, 8)),
+        self.assign(self.add_ir(ExprInt(1, 8)),
                     ExprId("status", 32))
-        self.affect(t_size(m2_csts.EXCEPT_UNK_MNEMO),
+        self.assign(t_size(m2_csts.EXCEPT_UNK_MNEMO),
                     m2_exception_flag)
         offset = self.llvm_context.ir_arch.loc_db.get_location_offset(asmblock.loc_key)
         self.set_ret(LLVMType.IntType(64)(offset))
@@ -1512,7 +1512,7 @@ class LLVMFunction(object):
             builder.position_at_end(self.get_basic_block_by_loc_key(next_label))
 
             # Common code
-            self.affect(self.add_ir(ExprInt(0, 8)),
+            self.assign(self.add_ir(ExprInt(0, 8)),
                         ExprId("status", 32))
 
             # Check if IRDst has been set
@@ -1535,8 +1535,8 @@ class LLVMFunction(object):
             builder.position_at_end(then_block)
             PC = self.llvm_context.PC
             to_ret = self.add_ir(codegen.delay_slot_dst)
-            self.affect(to_ret, PC)
-            self.affect(self.add_ir(ExprInt(0, 8)),
+            self.assign(to_ret, PC)
+            self.assign(self.add_ir(ExprInt(0, 8)),
                         ExprId("status", 32))
             self.set_ret(to_ret)
 
@@ -1545,7 +1545,7 @@ class LLVMFunction(object):
             PC = self.llvm_context.PC
             next_label_offset = self.llvm_context.ir_arch.loc_db.get_location_offset(next_label)
             to_ret = LLVMType.IntType(PC.size)(next_label_offset)
-            self.affect(to_ret, PC)
+            self.assign(to_ret, PC)
             self.set_ret(to_ret)
 
     def from_asmblock(self, asmblock):
diff --git a/test/analysis/data_flow.py b/test/analysis/data_flow.py
index 8682119d..2d4e2275 100644
--- a/test/analysis/data_flow.py
+++ b/test/analysis/data_flow.py
@@ -217,7 +217,7 @@ for irb in [G5_EXP_IRB0, G5_EXP_IRB1, G5_EXP_IRB2,
             G5_EXP_IRB3, G5_EXP_IRB4, G5_EXP_IRB5]:
     G5_EXP_IRA.add_irblock(irb)
 
-# graph 6 : Natural loop with dead variables symmetric affectation
+# graph 6 : Natural loop with dead variables symmetric assignment
 # (a = b <-> b = a )
 
 G6_IRA = IRA.new_ircfg()
@@ -344,7 +344,7 @@ G9_EXP_IRB4 = gen_irblock(LBL4, [[], [ExprAssign(r, b)]])
 for irb in [G9_EXP_IRB0, G9_EXP_IRB1, G9_EXP_IRB2, G9_EXP_IRB3, G9_EXP_IRB4]:
     G9_EXP_IRA.add_irblock(irb)
 
-# graph 10 : Natural loop with alive variables symmetric affectation
+# graph 10 : Natural loop with alive variables symmetric assignment
 # (a = b <-> b = a )
 
 G10_IRA = IRA.new_ircfg()