diff options
| -rw-r--r-- | miasm2/arch/arm/arch.py | 12 | ||||
| -rw-r--r-- | test/arch/arm/arch.py | 4 |
2 files changed, 12 insertions, 4 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index e7c5d535..7529b483 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -2,6 +2,7 @@ #-*- coding:utf-8 -*- import logging +from pdb import pm from pyparsing import * from miasm2.expression.expression import * from miasm2.core.cpu import * @@ -1806,13 +1807,18 @@ class armt_reg_wb(arm_reg_wb): def decode(self, v): v = v & self.lmask e = self.reg_info.expr[v] - e = ExprOp('wback', e) + if not e in self.parent.trlist.expr.args: + e = ExprOp('wback', e) self.expr = e return True def encode(self): e = self.expr - self.value = self.reg_info.expr.index(e.args[0]) + if isinstance(e, ExprOp): + if e.op != 'wback': + return False + e = e.args[0] + self.value = self.reg_info.expr.index(e) return True @@ -1877,7 +1883,7 @@ tswi_i = bs(l=8, cls=(arm_imm,), fname="swi_i") off8s = bs(l=8, cls=(arm_offs,), fname="offs") trlistpclr = bs(l=8, cls=(armt_rlist_pclr,)) -trlist = bs(l=8, cls=(armt_rlist,)) +trlist = bs(l=8, cls=(armt_rlist,), fname="trlist", order = -1) rbl_wb = bs(l=3, cls=(armt_reg_wb,), fname='rb') diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index 964d7295..f8912a5e 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -397,8 +397,10 @@ reg_tests_armt = [ ("00220f44 PUSH {R2, R3}", "0cb4"), - ("00076c54 LDMIA R1!, {R0, R1}", + ("00076c54 LDMIA R1, {R0, R1}", "03c9"), + ("XXXXXXXX LDMIA R5!, {R0-R3}", + "0fcd"), ("000a1c16 STMIA R6!, {R0-R3}", "0fc6"), |