about summary refs log tree commit diff stats
diff options
context:
space:
mode:
-rw-r--r--miasm2/arch/mips32/regs.py1
-rw-r--r--miasm2/jitter/jitcore_llvm.py3
2 files changed, 3 insertions, 1 deletions
diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py
index 0f065371..bf4926a8 100644
--- a/miasm2/arch/mips32/regs.py
+++ b/miasm2/arch/mips32/regs.py
@@ -47,6 +47,7 @@ regs_fcc_expr, regs_fcc_init, fccregs = gen_regs(regs_fcc_str, globals())
 all_regs_ids = [PC] + gpregs_expr + regs_flt_expr + regs_fcc_expr
 all_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids])
 all_regs_ids_init = [PC_init] + gpregs_init + regs_flt_init + regs_fcc_init
+all_regs_ids_no_alias = all_regs_ids[:]
 
 regs_init = {}
 for i, r in enumerate(all_regs_ids):
diff --git a/miasm2/jitter/jitcore_llvm.py b/miasm2/jitter/jitcore_llvm.py
index 7dc2f0c4..03bfb90b 100644
--- a/miasm2/jitter/jitcore_llvm.py
+++ b/miasm2/jitter/jitcore_llvm.py
@@ -16,7 +16,8 @@ class JitCore_LLVM(jitcore.JitCore):
     # Architecture dependant libraries
     arch_dependent_libs = {"x86": "JitCore_x86.so",
                            "arm": "JitCore_arm.so",
-                           "msp430": "JitCore_msp430.so"}
+                           "msp430": "JitCore_msp430.so",
+                           "mips32": "JitCore_mips32.so"}
 
     def __init__(self, my_ir, bs=None):
         super(JitCore_LLVM, self).__init__(my_ir, bs)