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-rw-r--r--.codespell_ignore1
-rw-r--r--README.md7
-rw-r--r--miasm/analysis/gdbserver.py4
-rw-r--r--miasm/arch/arm/sem.py72
-rw-r--r--miasm/arch/mep/sem.py2
-rw-r--r--miasm/arch/mips32/sem.py2
-rw-r--r--miasm/arch/ppc/sem.py18
-rw-r--r--miasm/arch/x86/arch.py2
-rw-r--r--miasm/expression/expression.py4
-rw-r--r--miasm/ir/ir.py2
-rw-r--r--miasm/ir/symbexec.py2
-rw-r--r--miasm/ir/translators/z3_ir.py2
-rw-r--r--miasm/jitter/bn.h2
-rw-r--r--miasm/loader/pe.py6
-rw-r--r--miasm/os_dep/linux/syscall.py2
-rw-r--r--miasm/os_dep/win_api_x86_32.py30
-rw-r--r--test/utils/testset.py2
17 files changed, 77 insertions, 83 deletions
diff --git a/.codespell_ignore b/.codespell_ignore
index a7423acd..5e7feec6 100644
--- a/.codespell_ignore
+++ b/.codespell_ignore
@@ -10,3 +10,4 @@ daa
 od
 blocs
 fpr
+seh
diff --git a/README.md b/README.md
index a4c55a20..f80d02a3 100644
--- a/README.md
+++ b/README.md
@@ -616,10 +616,3 @@ Books
 
 * [Practical Reverse Engineering: X86, X64, Arm, Windows Kernel, Reversing Tools, and Obfuscation](http://eu.wiley.com/WileyCDA/WileyTitle/productCd-1118787315,subjectCd-CSJ0.html): Introduction to Miasm (Chapter 5 "Obfuscation")
 * [BlackHat Python - Appendix](https://github.com/oreilly-japan/black-hat-python-jp-support/tree/master/appendix-A): Japan security book's samples
-
-
-Misc
-====
-
-* Man, does miasm has a link with rr0d?
-* Yes! crappy code and uggly documentation.
diff --git a/miasm/analysis/gdbserver.py b/miasm/analysis/gdbserver.py
index ac58cdad..b45e9f35 100644
--- a/miasm/analysis/gdbserver.py
+++ b/miasm/analysis/gdbserver.py
@@ -251,8 +251,8 @@ class GdbServer(object):
                     else:
                         raise NotImplementedError("Unknown Except")
                 elif isinstance(ret, debugging.DebugBreakpointTerminate):
-                    # Connexion should close, but keep it running as a TRAP
-                    # The connexion will be close on instance destruction
+                    # Connection should close, but keep it running as a TRAP
+                    # The connection will be close on instance destruction
                     print(ret)
                     self.status = b"S05"
                     self.send_queue.append(b"S05")
diff --git a/miasm/arch/arm/sem.py b/miasm/arch/arm/sem.py
index a0ee8d66..7d72b956 100644
--- a/miasm/arch/arm/sem.py
+++ b/miasm/arch/arm/sem.py
@@ -39,18 +39,18 @@ coproc_reg_dict = {
         ("p15", "c0", 1, "c0", 7): AIDR,
 
         ("p15", "c0", 2, "c0", 0): CSSELR,
-        
+
         ("p15", "c0", 4, "c0", 0): VPIDR,
         ("p15", "c0", 4, "c0", 5): VMPIDR,
 
         ("p15", "c1", 0, "c0", 0): SCTLR,
         ("p15", "c1", 0, "c0", 1): ACTLR,
         ("p15", "c1", 0, "c0", 2): CPACR,
-        
+
         ("p15", "c1", 0, "c1", 0): SCR,
         ("p15", "c1", 0, "c1", 1): SDER,
         ("p15", "c1", 0, "c1", 2): NSACR,
-        
+
         ("p15", "c1", 4, "c0", 0): HSCTLR,
         ("p15", "c1", 4, "c0", 1): HACTLR,
 
@@ -59,16 +59,16 @@ coproc_reg_dict = {
         ("p15", "c1", 4, "c1", 2): HCPTR,
         ("p15", "c1", 4, "c1", 3): HSTR,
         ("p15", "c1", 4, "c1", 7): HACR,
-        
+
         # TODO: TTBRO/TTBR1 64-bit
-        ("p15", "c2", 0, "c0", 0): TTBR0, 
+        ("p15", "c2", 0, "c0", 0): TTBR0,
         ("p15", "c2", 0, "c0", 1): TTBR1,
         ("p15", "c2", 0, "c0", 2): TTBCR,
 
         ("p15", "c2", 4, "c0", 2): HTCR,
-        
+
         ("p15", "c2", 4, "c1", 2): VTCR,
-        
+
         # TODO: HTTBR, VTTBR
 
         ("p15", "c3", 0, "c0", 0): DACR,
@@ -81,7 +81,7 @@ coproc_reg_dict = {
 
         ("p15", "c5", 4, "c1", 0): HADFSR,
         ("p15", "c5", 4, "c1", 1): HAIFSR,
-        
+
         ("p15", "c5", 4, "c2", 0): HSR,
 
         ("p15", "c6", 0, "c1", 0): DFAR,
@@ -90,12 +90,12 @@ coproc_reg_dict = {
         ("p15", "c6", 4, "c0", 0): HDFAR,
         ("p15", "c6", 4, "c0", 2): HIFAR,
         ("p15", "c6", 4, "c0", 4): HPFAR,
-        
+
         ("p15", "c7", 0, "c1", 0): ICIALLUIS,
         ("p15", "c7", 0, "c1", 6): BPIALLIS,
-        
+
         ("p15", "c7", 0, "c4", 0): PAR,
-        
+
         # TODO: PAR 64-bit
 
         ("p15", "c7", 0, "c5", 0): ICIALLU,
@@ -103,10 +103,10 @@ coproc_reg_dict = {
         ("p15", "c7", 0, "c5", 4): CP15ISB,
         ("p15", "c7", 0, "c5", 6): BPIALL,
         ("p15", "c7", 0, "c5", 7): BPIMVA,
-        
+
         ("p15", "c7", 0, "c6", 1): DCIMVAC,
         ("p15", "c7", 0, "c6", 2): DCISW,
-        
+
         ("p15", "c7", 0, "c8", 0): ATS1CPR,
         ("p15", "c7", 0, "c8", 1): ATS1CPW,
         ("p15", "c7", 0, "c8", 2): ATS1CUR,
@@ -115,33 +115,33 @@ coproc_reg_dict = {
         ("p15", "c7", 0, "c8", 5): ATS12NSOPW,
         ("p15", "c7", 0, "c8", 6): ATS12NSOUR,
         ("p15", "c7", 0, "c8", 7): ATS12NSOUW,
-        
+
         ("p15", "c7", 0, "c10", 1): DCCMVAC,
         ("p15", "c7", 0, "c10", 2): DCCSW,
         ("p15", "c7", 0, "c10", 4): CP15DSB,
         ("p15", "c7", 0, "c10", 5): CP15DMB,
-        
+
         ("p15", "c7", 0, "c11", 1): DCCMVAU,
-        
+
         ("p15", "c7", 0, "c14", 1): DCCIMVAC,
         ("p15", "c7", 0, "c14", 2): DCCISW,
-        
+
         ("p15", "c7", 4, "c8", 0): ATS1HR,
         ("p15", "c7", 4, "c8", 1): ATS1HW,
-        
+
         ("p15", "c8", 0, "c3", 0): TLBIALLIS,
         ("p15", "c8", 0, "c3", 1): TLBIMVAIS,
         ("p15", "c8", 0, "c3", 2): TLBIASIDIS,
         ("p15", "c8", 0, "c3", 3): TLBIMVAAIS,
-        
+
         ("p15", "c8", 0, "c5", 0): ITLBIALL,
         ("p15", "c8", 0, "c5", 1): ITLBIMVA,
         ("p15", "c8", 0, "c5", 2): ITLBIASID,
-        
+
         ("p15", "c8", 0, "c6", 0): DTLBIALL,
         ("p15", "c8", 0, "c6", 1): DTLBIMVA,
         ("p15", "c8", 0, "c6", 2): DTLBIASID,
-        
+
         ("p15", "c8", 0, "c7", 0): TLBIALL,
         ("p15", "c8", 0, "c7", 1): TLBIMVA,
         ("p15", "c8", 0, "c7", 2): TLBIASID,
@@ -150,11 +150,11 @@ coproc_reg_dict = {
         ("p15", "c8", 4, "c3", 0): TLBIALLHIS,
         ("p15", "c8", 4, "c3", 1): TLBIMVAHIS,
         ("p15", "c8", 4, "c3", 4): TLBIALLNSNHIS,
-        
+
         ("p15", "c8", 4, "c7", 0): TLBIALLH,
         ("p15", "c8", 4, "c7", 1): TLBIMVAH,
         ("p15", "c8", 4, "c7", 2): TLBIALLNSNH,
-        
+
         ("p15", "c9", 0, "c12", 0): PMCR,
         ("p15", "c9", 0, "c12", 1): PMCNTENSET,
         ("p15", "c9", 0, "c12", 2): PMCNTENCLR,
@@ -163,16 +163,16 @@ coproc_reg_dict = {
         ("p15", "c9", 0, "c12", 5): PMSELR,
         ("p15", "c9", 0, "c12", 6): PMCEID0,
         ("p15", "c9", 0, "c12", 7): PMCEID1,
-        
+
         ("p15", "c9", 0, "c13", 0): PMCCNTR,
         ("p15", "c9", 0, "c13", 1): PMXEVTYPER,
         ("p15", "c9", 0, "c13", 2): PMXEVCNTR,
-        
+
         ("p15", "c9", 0, "c14", 0): PMUSERENR,
         ("p15", "c9", 0, "c14", 1): PMINTENSET,
         ("p15", "c9", 0, "c14", 2): PMINTENCLR,
         ("p15", "c9", 0, "c14", 3): PMOVSSET,
-        
+
         ("p15", "c10", 0, "c2", 0): PRRR,   # ALIAS MAIR0
         ("p15", "c10", 0, "c2", 1): NMRR,   # ALIAS MAIR1
 
@@ -191,33 +191,33 @@ coproc_reg_dict = {
         ("p15", "c12", 0, "c1", 0): ISR,
 
         ("p15", "c12", 4, "c0", 0): HVBAR,
-        
+
         ("p15", "c13", 0, "c0", 0): FCSEIDR,
         ("p15", "c13", 0, "c0", 1): CONTEXTIDR,
         ("p15", "c13", 0, "c0", 2): TPIDRURW,
         ("p15", "c13", 0, "c0", 3): TPIDRURO,
         ("p15", "c13", 0, "c0", 4): TPIDRPRW,
-        
+
         ("p15", "c13", 4, "c0", 2): HTPIDR,
-        
+
         ("p15", "c14", 0, "c0", 0): CNTFRQ,
         # TODO: CNTPCT 64-bit
-        
+
         ("p15", "c14", 0, "c1", 0): CNTKCTL,
-        
+
         ("p15", "c14", 0, "c2", 0): CNTP_TVAL,
         ("p15", "c14", 0, "c2", 1): CNTP_CTL,
-        
+
         ("p15", "c14", 0, "c3", 0): CNTV_TVAL,
         ("p15", "c14", 0, "c3", 1): CNTV_CTL,
-        
+
         # TODO: CNTVCT, CNTP_CVAL, CNTV_CVAL, CNTVOFF 64-bit
-        
+
         ("p15", "c14", 4, "c1", 0): CNTHCTL,
 
         ("p15", "c14", 4, "c2", 0): CNTHP_TVAL,
         ("p15", "c14", 4, "c2", 0): CNTHP_CTL
-        
+
         # TODO: CNTHP_CVAL 64-bit
         }
 
@@ -2014,7 +2014,7 @@ class ir_arml(IntermediateRepresentation):
             index += 1
             instr = block.lines[index]
 
-            # Add conditionnal jump to current irblock
+            # Add conditional jump to current irblock
             loc_do = self.loc_db.add_location()
             loc_next = self.get_next_loc_key(instr)
 
diff --git a/miasm/arch/mep/sem.py b/miasm/arch/mep/sem.py
index c1585d35..df484ab5 100644
--- a/miasm/arch/mep/sem.py
+++ b/miasm/arch/mep/sem.py
@@ -334,7 +334,7 @@ if False:
 def sltu3(r0, rn, rm_or_imm5):
     """SLTU3 - Set on less than (unsigned)."""
 
-    # if (Rn<Rm) R0<-1 else R0<-0 (Unigned)
+    # if (Rn<Rm) R0<-1 else R0<-0 (Unsigned)
     # if (Rn<ZeroExt(imm5)) R0<-1 else R0<-0(Unsigned)
     r0 = i32(1) if compute_u_inf(rn, rm_or_imm5) else i32(0)
 
diff --git a/miasm/arch/mips32/sem.py b/miasm/arch/mips32/sem.py
index 903be3be..5032432c 100644
--- a/miasm/arch/mips32/sem.py
+++ b/miasm/arch/mips32/sem.py
@@ -68,7 +68,7 @@ def lbu(arg1, arg2):
 
 @sbuild.parse
 def lh(arg1, arg2):
-    """A word is loaded into a register @arg1 from the 
+    """A word is loaded into a register @arg1 from the
     specified address @arg2."""
     arg1 = mem16[arg2.ptr].signExtend(32)
 
diff --git a/miasm/arch/ppc/sem.py b/miasm/arch/ppc/sem.py
index 61330fe1..7ca7e3e1 100644
--- a/miasm/arch/ppc/sem.py
+++ b/miasm/arch/ppc/sem.py
@@ -26,17 +26,17 @@ sr_dict = {
 }
 
 float_dict = {
-    0: FPR0, 1: FPR1, 2: FPR2, 3: FPR3, 4: FPR4, 5: FPR5, 6: FPR6, 7: FPR7, 8: FPR8, 
-    9: FPR9, 10: FPR10, 11: FPR11, 12: FPR12, 13: FPR13, 14: FPR14, 15: FPR15, 16: FPR16, 
-    17: FPR17, 18: FPR18, 19: FPR19, 20: FPR20, 21: FPR21, 22: FPR22, 23: FPR23, 24: FPR24, 
+    0: FPR0, 1: FPR1, 2: FPR2, 3: FPR3, 4: FPR4, 5: FPR5, 6: FPR6, 7: FPR7, 8: FPR8,
+    9: FPR9, 10: FPR10, 11: FPR11, 12: FPR12, 13: FPR13, 14: FPR14, 15: FPR15, 16: FPR16,
+    17: FPR17, 18: FPR18, 19: FPR19, 20: FPR20, 21: FPR21, 22: FPR22, 23: FPR23, 24: FPR24,
     25: FPR25, 26: FPR26, 27: FPR27, 28: FPR28, 29: FPR29, 30: FPR30, 31: FPR31
 }
 
 vex_dict = {
-    0: VR0, 1: VR1, 2: VR2, 3: VR3, 4: VR4, 5: VR5, 6: VR6, 7: VR7, 8: VR8, 
-    9: VR9, 10: VR10, 11: VR11, 12: VR12, 13: VR13, 14: VR14, 15: VR15, 16: VR16, 
-    17: VR17, 18: VR18, 19: VR19, 20: VR20, 21: VR21, 22: VR22, 23: VR23, 24: VR24, 
-    25: VR25, 26: VR26, 27: VR27, 28: VR28, 29: VR29, 30: VR30, 31: VR31,    
+    0: VR0, 1: VR1, 2: VR2, 3: VR3, 4: VR4, 5: VR5, 6: VR6, 7: VR7, 8: VR8,
+    9: VR9, 10: VR10, 11: VR11, 12: VR12, 13: VR13, 14: VR14, 15: VR15, 16: VR16,
+    17: VR17, 18: VR18, 19: VR19, 20: VR20, 21: VR21, 22: VR22, 23: VR23, 24: VR24,
+    25: VR25, 26: VR26, 27: VR27, 28: VR28, 29: VR29, 30: VR30, 31: VR31,
 }
 
 crf_dict = dict((ExprId("CR%d" % i, 4),
@@ -265,7 +265,7 @@ def mn_do_load(ir, instr, arg1, arg2, arg3=None):
         return  [], []
     elif instr.name[1] == 'V':
         print("Warning, instruction %s implemented as NOP" % instr)
-        return [], []    
+        return [], []
 
     size = {'B': 8, 'H': 16, 'W': 32}[instr.name[1]]
 
@@ -527,7 +527,7 @@ def mn_do_rfi(ir, instr):
     ret = [ ExprAssign(MSR, (MSR &
                           ~ExprInt(0b1111111101110011, 32) |
                           ExprCompose(SRR1[0:2], ExprInt(0, 2),
-                                      SRR1[4:7], ExprInt(0, 1), 
+                                      SRR1[4:7], ExprInt(0, 1),
                                       SRR1[8:16], ExprInt(0, 16)))),
             ExprAssign(PC, dest),
             ExprAssign(ir.IRDst, dest) ]
diff --git a/miasm/arch/x86/arch.py b/miasm/arch/x86/arch.py
index 725f3126..d1802045 100644
--- a/miasm/arch/x86/arch.py
+++ b/miasm/arch/x86/arch.py
@@ -547,7 +547,7 @@ class instruction_x86(instruction):
 
     def __str__(self):
         return self.to_string()
-      
+
     def to_string(self, loc_db=None):
         o = super(instruction_x86, self).to_string(loc_db)
         if self.additional_info.g1.value & 1:
diff --git a/miasm/expression/expression.py b/miasm/expression/expression.py
index ef05a2b6..c2bf5b8b 100644
--- a/miasm/expression/expression.py
+++ b/miasm/expression/expression.py
@@ -727,8 +727,8 @@ class Expr(object):
 
     def visit(self, callback):
         """
-        Apply callbak to all sub expression of @self
-        This function keeps a cache to avoid rerunning @callbak on common sub
+        Apply callback to all sub expression of @self
+        This function keeps a cache to avoid rerunning @callback on common sub
         expressions.
 
         @callback: fn(Expr) -> Expr
diff --git a/miasm/ir/ir.py b/miasm/ir/ir.py
index 9b2e4ba0..3219b5fc 100644
--- a/miasm/ir/ir.py
+++ b/miasm/ir/ir.py
@@ -885,7 +885,7 @@ class IntermediateRepresentation(object):
         return irblock
 
     def is_pc_written(self, block):
-        """Return the first Assignblk of the @blockin which PC is written
+        """Return the first Assignblk of the @block in which PC is written
         @block: IRBlock instance"""
         all_pc = viewvalues(self.arch.pc)
         for assignblk in block:
diff --git a/miasm/ir/symbexec.py b/miasm/ir/symbexec.py
index 65ddde3b..8c6245b8 100644
--- a/miasm/ir/symbexec.py
+++ b/miasm/ir/symbexec.py
@@ -121,7 +121,7 @@ class MemArray(MutableMapping):
     content relatively to an integer offset from *base*.
 
     The value associated to a given offset is a description of the slice of a
-    stored expression. The slice size depends on the configutation of the
+    stored expression. The slice size depends on the configuration of the
     MemArray. For example, for a slice size of 8 bits, the assignment:
     - @32[EAX+0x10] = EBX
 
diff --git a/miasm/ir/translators/z3_ir.py b/miasm/ir/translators/z3_ir.py
index 6b706770..1a36e94e 100644
--- a/miasm/ir/translators/z3_ir.py
+++ b/miasm/ir/translators/z3_ir.py
@@ -15,7 +15,7 @@ log.addHandler(console_handler)
 log.setLevel(logging.WARNING)
 
 class Z3Mem(object):
-    """Memory abstration for TranslatorZ3. Memory elements are only accessed,
+    """Memory abstraction for TranslatorZ3. Memory elements are only accessed,
     never written. To give a concrete value for a given memory cell in a solver,
     add "mem32.get(address, size) == <value>" constraints to your equation.
     The endianness of memory accesses is handled accordingly to the "endianness"
diff --git a/miasm/jitter/bn.h b/miasm/jitter/bn.h
index 1aa6b432..8c4a8ba1 100644
--- a/miasm/jitter/bn.h
+++ b/miasm/jitter/bn.h
@@ -35,7 +35,7 @@ Code slightly modified to support ast generation calculus style from Expr.
 #include <assert.h>
 
 
-/* This macro defines the word size in bytes of the array that constitues the big-number data structure. */
+/* This macro defines the word size in bytes of the array that constitutes the big-number data structure. */
 #ifndef WORD_SIZE
   #define WORD_SIZE 4
 #endif
diff --git a/miasm/loader/pe.py b/miasm/loader/pe.py
index c402715a..2d257906 100644
--- a/miasm/loader/pe.py
+++ b/miasm/loader/pe.py
@@ -1326,7 +1326,7 @@ class DirRes(CStruct):
                     # data dir
                     off = entry.offsettodata
                     if not 0 <= off < len(raw):
-                        log.warn('bad resrouce entry')
+                        log.warn('bad resource entry')
                         continue
                     data = ResDataEntry.unpack(raw,
                                                off,
@@ -1340,7 +1340,7 @@ class DirRes(CStruct):
                     log.warn('warning recusif subdir')
                     continue
                 if not 0 <= off < len(self.parent_head.img_rva):
-                    log.warn('bad resrouce entry')
+                    log.warn('bad resource entry')
                     continue
                 subdir, length = ResDesc_e.unpack_l(raw,
                                                     off,
@@ -1352,7 +1352,7 @@ class DirRes(CStruct):
                                                      ResEntry,
                                                      nbr)
                 except RuntimeError:
-                    log.warn('bad resrouce entry')
+                    log.warn('bad resource entry')
                     continue
 
                 entry.subdir = subdir
diff --git a/miasm/os_dep/linux/syscall.py b/miasm/os_dep/linux/syscall.py
index 3b1275aa..acebe2cb 100644
--- a/miasm/os_dep/linux/syscall.py
+++ b/miasm/os_dep/linux/syscall.py
@@ -681,7 +681,7 @@ def sys_x86_64_connect(jitter, linux_env):
     log.debug("sys_connect(%x, %r, %x)", fd, raddr, addrlen)
 
     # Stub
-    # Always refuse the connexion
+    # Always refuse the connection
     jitter.cpu.RAX = -1
 
 
diff --git a/miasm/os_dep/win_api_x86_32.py b/miasm/os_dep/win_api_x86_32.py
index 9d86e833..46f5783c 100644
--- a/miasm/os_dep/win_api_x86_32.py
+++ b/miasm/os_dep/win_api_x86_32.py
@@ -3156,7 +3156,7 @@ class FLS(object):
         '''
         DWORD FlsAlloc(
           PFLS_CALLBACK_FUNCTION lpCallback
-        );    
+        );
         '''
         ret_ad, args = jitter.func_args_stdcall(["lpCallback"])
         index = len(self.slots)
@@ -3173,7 +3173,7 @@ class FLS(object):
         ret_ad, args = jitter.func_args_stdcall(["dwFlsIndex", "lpFlsData"])
         self.slots[args.dwFlsIndex] = args.lpFlsData
         jitter.func_ret_stdcall(ret_ad, 1)
-        
+
     def kernel32_FlsGetValue(self, jitter):
         '''
         PVOID FlsGetValue(
@@ -3181,8 +3181,8 @@ class FLS(object):
         );
         '''
         ret_ad, args = jitter.func_args_stdcall(["dwFlsIndex"])
-        jitter.func_ret_stdcall(ret_ad, self.slots[args.dwFlsIndex])        
-        
+        jitter.func_ret_stdcall(ret_ad, self.slots[args.dwFlsIndex])
+
 fls = FLS()
 
 
@@ -3205,15 +3205,15 @@ def kernel32_GetStdHandle(jitter):
     HANDLE WINAPI GetStdHandle(
       _In_ DWORD nStdHandle
     );
-    
-    STD_INPUT_HANDLE (DWORD)-10 	
+
+    STD_INPUT_HANDLE (DWORD)-10
     The standard input device. Initially, this is the console input buffer, CONIN$.
 
-    STD_OUTPUT_HANDLE (DWORD)-11 	
+    STD_OUTPUT_HANDLE (DWORD)-11
     The standard output device. Initially, this is the active console screen buffer, CONOUT$.
 
-    STD_ERROR_HANDLE (DWORD)-12 	
-    The standard error device. Initially, this is the active console screen buffer, CONOUT$.    
+    STD_ERROR_HANDLE (DWORD)-12
+    The standard error device. Initially, this is the active console screen buffer, CONOUT$.
     '''
     ret_ad, args = jitter.func_args_stdcall(["nStdHandle"])
     jitter.func_ret_stdcall(ret_ad, {
@@ -3222,7 +3222,7 @@ def kernel32_GetStdHandle(jitter):
         STD_INPUT_HANDLE: 3,
     }[args.nStdHandle])
 
-    
+
 FILE_TYPE_UNKNOWN = 0x0000
 FILE_TYPE_CHAR = 0x0002
 
@@ -3302,13 +3302,13 @@ def kernel32_IsProcessorFeaturePresent(jitter):
         17: False,
     }[args.ProcessorFeature])
 
-    
+
 def kernel32_GetACP(jitter):
     '''
     UINT GetACP();
     '''
     ret_ad, args = jitter.func_args_stdcall([])
-    # Windows-1252: Latin 1 / Western European  Superset of ISO-8859-1 (without C1 controls). 
+    # Windows-1252: Latin 1 / Western European  Superset of ISO-8859-1 (without C1 controls).
     jitter.func_ret_stdcall(ret_ad, 1252)
 
 
@@ -3333,7 +3333,7 @@ def kernel32_IsValidCodePage(jitter):
     );
     '''
     ret_ad, args = jitter.func_args_stdcall(["CodePage"])
-    jitter.func_ret_stdcall(ret_ad, args.CodePage in VALID_CODE_PAGES)    
+    jitter.func_ret_stdcall(ret_ad, args.CodePage in VALID_CODE_PAGES)
 
 
 def kernel32_GetCPInfo(jitter):
@@ -3346,8 +3346,8 @@ def kernel32_GetCPInfo(jitter):
     ret_ad, args = jitter.func_args_stdcall(["CodePage", "lpCPInfo"])
     assert args.CodePage == 1252
     # ref: http://www.rensselaer.org/dept/cis/software/g77-mingw32/include/winnls.h
-    #define MAX_LEADBYTES 	12
+    #define MAX_LEADBYTES       12
     #define MAX_DEFAULTCHAR	2
     jitter.vm.set_mem(args.lpCPInfo, struct.pack('<I', 0x1) + b'??' + b'\x00' * 12)
     jitter.func_ret_stdcall(ret_ad, 1)
-    
+
diff --git a/test/utils/testset.py b/test/utils/testset.py
index eee0e6f7..2bdb7450 100644
--- a/test/utils/testset.py
+++ b/test/utils/testset.py
@@ -203,7 +203,7 @@ class TestSet(object):
             try:
                 os.remove(product)
             except OSError:
-                print("Cleanning error: Unable to remove %s" % product)
+                print("Cleaning error: Unable to remove %s" % product)
 
     def add_additional_args(self, args):
         """Add arguments to used on the test command line