diff options
45 files changed, 167 insertions, 298 deletions
diff --git a/README.md b/README.md index 2ad1a3e8..e3f16159 100644 --- a/README.md +++ b/README.md @@ -165,8 +165,8 @@ Disassembling the shellcode at address `0`: >>> from miasm2.analysis.machine import Machine >>> machine = Machine('x86_32') >>> mdis = machine.dis_engine(c.bin_stream) ->>> blocks = mdis.dis_multiblock(0) ->>> for block in blocks.blocks: +>>> asmcfg = mdis.dis_multiblock(0) +>>> for block in asmcfg.blocks: ... print block ... loc_0000000000000000:0x00000000 @@ -217,8 +217,7 @@ def code_sentinelle(jitter): Active logs: ``` ->>> jitter.jit.log_regs = True ->>> jitter.jit.log_mn = True +>>> jitter.set_trace_log() ``` Run at arbitrary address: @@ -269,7 +268,7 @@ Initializing the IR pool: ``` >>> ira = machine.ira() ->>> for block in blocks.blocks +>>> for block in asmcfg.blocks: ... ira.add_block(block) ... ``` diff --git a/example/disasm/file.py b/example/disasm/file.py index 88ba6162..196e1b1a 100644 --- a/example/disasm/file.py +++ b/example/disasm/file.py @@ -13,6 +13,6 @@ cont = Container.from_stream(open(sys.argv[1])) mdis = dis_x86_32(cont.bin_stream) # Inform the engine to avoid disassembling null instructions mdis.dont_dis_nulstart_bloc = True -blocks = mdis.dis_multiblock(addr) +asmcfg = mdis.dis_multiblock(addr) -open('graph.dot', 'w').write(blocks.dot()) +open('graph.dot', 'w').write(asmcfg.dot()) diff --git a/example/expression/simplification_tools.py b/example/expression/simplification_tools.py index 7c15b3e7..cb062fb3 100644 --- a/example/expression/simplification_tools.py +++ b/example/expression/simplification_tools.py @@ -32,7 +32,6 @@ x = ExprMem(a + b + ExprInt(0x42, 32), 32) def replace_expr(e): - # print 'visit', e dct = {c + ExprInt(0x42, 32): d, a + b: c, } if e in dct: diff --git a/example/ida/ctype_propagation.py b/example/ida/ctype_propagation.py index d35835dc..db324833 100644 --- a/example/ida/ctype_propagation.py +++ b/example/ida/ctype_propagation.py @@ -268,7 +268,6 @@ def analyse_function(): iraCallStackFixer = get_ira_call_fixer(ira) ir_arch = iraCallStackFixer(mdis.symbol_pool) - asmcfg = mdis.dis_multiblock(addr) # Generate IR for block in asmcfg.blocks: diff --git a/example/ida/graph_ir.py b/example/ida/graph_ir.py index 97d30851..dd842281 100644 --- a/example/ida/graph_ir.py +++ b/example/ida/graph_ir.py @@ -116,7 +116,6 @@ def build_graph(verbose=False, simplify=False): # populate symbols with ida names for addr, name in idautils.Names(): - # print hex(ad), repr(name) if name is None: continue if (mdis.symbol_pool.getby_offset(addr) or diff --git a/example/jitter/mips32.py b/example/jitter/mips32.py index c5b2f7f5..31ab03c8 100755 --- a/example/jitter/mips32.py +++ b/example/jitter/mips32.py @@ -5,16 +5,11 @@ from miasm2.analysis import debugging from miasm2.jitter.csts import * from miasm2.analysis.machine import Machine -from pdb import pm - parser = ArgumentParser( description="""Sandbox raw binary with mips32 engine (ex: jit_mips32.py example/mips32_sc_l.bin 0)""") -parser.add_argument("-r", "--log-regs", - help="Log registers value for each instruction", - action="store_true") -parser.add_argument("-m", "--log-mn", - help="Log desassembly conversion for each instruction", +parser.add_argument("-t", "--trace", + help="Log instructions/registers values", action="store_true") parser.add_argument("-n", "--log-newbloc", help="Log basic blocks processed by the Jitter", @@ -43,9 +38,11 @@ def jit_mips32_binary(args): myjit.init_stack() # Log level (if available with jitter engine) - myjit.jit.log_regs = args.log_regs - myjit.jit.log_mn = args.log_mn - myjit.jit.log_newbloc = args.log_newbloc + myjit.set_trace_log( + trace_instr=args.trace, + trace_regs=args.trace, + trace_new_blocks=args.log_newbloc + ) myjit.vm.add_memory_page(0, PAGE_READ | PAGE_WRITE, open(filepath).read()) myjit.add_breakpoint(0x1337BEEF, code_sentinelle) diff --git a/example/jitter/msp430.py b/example/jitter/msp430.py index 6dd67542..2f9b8649 100755 --- a/example/jitter/msp430.py +++ b/example/jitter/msp430.py @@ -8,11 +8,8 @@ from miasm2.analysis.machine import Machine parser = ArgumentParser( description="""Sandbox raw binary with msp430 engine (ex: jit_msp430.py example/msp430_sc.bin 0)""") -parser.add_argument("-r", "--log-regs", - help="Log registers value for each instruction", - action="store_true") -parser.add_argument("-m", "--log-mn", - help="Log desassembly conversion for each instruction", +parser.add_argument("-t", "--trace", + help="Log instructions/registers values", action="store_true") parser.add_argument("-n", "--log-newbloc", help="Log basic blocks processed by the Jitter", @@ -36,9 +33,11 @@ def jit_msp430_binary(args): myjit.init_stack() # Log level (if available with jitter engine) - myjit.jit.log_regs = args.log_regs - myjit.jit.log_mn = args.log_mn - myjit.jit.log_newbloc = args.log_newbloc + myjit.set_trace_log( + trace_instr=args.trace, + trace_regs=args.trace, + trace_new_blocks=args.log_newbloc + ) myjit.vm.add_memory_page(0, PAGE_READ | PAGE_WRITE, open(filepath, "rb").read()) myjit.add_breakpoint(0x1337, lambda _: exit(0)) diff --git a/example/jitter/x86_32.py b/example/jitter/x86_32.py index 1409d7aa..5272f732 100644 --- a/example/jitter/x86_32.py +++ b/example/jitter/x86_32.py @@ -24,8 +24,7 @@ data = open(args.filename).read() run_addr = 0x40000000 myjit.vm.add_memory_page(run_addr, PAGE_READ | PAGE_WRITE, data) -myjit.jit.log_regs = True -myjit.jit.log_mn = True +myjit.set_trace_log() myjit.push_uint32_t(0x1337beef) myjit.add_breakpoint(0x1337beef, code_sentinelle) diff --git a/miasm2/analysis/data_analysis.py b/miasm2/analysis/data_analysis.py index 5e88665e..0782c12c 100644 --- a/miasm2/analysis/data_analysis.py +++ b/miasm2/analysis/data_analysis.py @@ -4,7 +4,6 @@ from miasm2.ir.symbexec import SymbolicExecutionEngine def get_node_name(label, i, n): - # n_name = "%s_%d_%s"%(label.name, i, n) n_name = (label, i, n) return n_name @@ -69,18 +68,12 @@ def intra_block_flow_symbexec(ir_arch, flow_graph, irb, in_nodes, out_nodes): sb = SymbolicExecutionEngine(ir_arch, dict(symbols_init)) sb.emulbloc(irb) - # print "*"*40 - # print irb - # print sb.dump_id() - # print sb.dump_mem() for n_w in sb.symbols: - # print n_w v = sb.symbols[n_w] if n_w in symbols_init and symbols_init[n_w] == v: continue read_values = v.get_r(cst_read=True) - # print n_w, v, [str(x) for x in read_values] node_n_w = get_node_name(irb.loc_key, len(irb), n_w) for n_r in read_values: @@ -97,9 +90,6 @@ def intra_block_flow_symbexec(ir_arch, flow_graph, irb, in_nodes, out_nodes): def inter_block_flow_link(ir_arch, flow_graph, irb_in_nodes, irb_out_nodes, todo, link_exec_to_data): lbl, current_nodes, exec_nodes = todo - # print 'TODO' - # print lbl - # print [(str(x[0]), str(x[1])) for x in current_nodes] current_nodes = dict(current_nodes) # link current nodes to bloc in_nodes @@ -107,12 +97,10 @@ def inter_block_flow_link(ir_arch, flow_graph, irb_in_nodes, irb_out_nodes, todo print "cannot find bloc!!", lbl return set() irb = ir_arch.blocks[lbl] - # pp(('IN', lbl, [(str(x[0]), str(x[1])) for x in current_nodes.items()])) to_del = set() for n_r, node_n_r in irb_in_nodes[irb.loc_key].items(): if not n_r in current_nodes: continue - # print 'add link', current_nodes[n_r], node_n_r flow_graph.add_uniq_edge(current_nodes[n_r], node_n_r) to_del.add(n_r) @@ -137,8 +125,6 @@ def inter_block_flow_link(ir_arch, flow_graph, irb_in_nodes, irb_out_nodes, todo for lbl_dst in ir_arch.graph.successors(irb.loc_key): todo.add((lbl_dst, tuple(current_nodes.items()), x_nodes)) - # pp(('OUT', lbl, [(str(x[0]), str(x[1])) for x in current_nodes.items()])) - return todo @@ -161,18 +147,11 @@ def create_implicit_flow(ir_arch, flow_graph, irb_in_nodes, irb_out_ndes): if not isinstance(n_r, ExprId): continue - # print "###", n_r - # print "###", irb - # print "###", 'OUT', [str(x) for x in irb.out_nodes] - # print "###", irb_son - # print "###", 'IN', [str(x) for x in irb_son.in_nodes] - node_n_w = irb.loc_key, len(irb), n_r irb_out_nodes[irb.loc_key][n_r] = node_n_w if not n_r in irb_in_nodes[irb.loc_key]: irb_in_nodes[irb.loc_key][n_r] = irb.loc_key, 0, n_r node_n_r = irb_in_nodes[irb.loc_key][n_r] - # print "###", node_n_r for lbl_p in ir_arch.graph.predecessors(irb.loc_key): todo.add(lbl_p) @@ -220,46 +199,11 @@ class symb_exec_func: b = self.ir_arch.get_block(ad) if b is None: raise ValueError("unknown bloc! %s" % ad) - """ - dead = b.dead[0] - for d in dead: - if d in variables: - del(variables[d]) - """ variables = variables.items() s = parent, ad, tuple(sorted(variables)) - """ - state_var = s[1] - if s in self.states_var_done: - print 'skip state' - return - if not ad in self.stateby_ad: - self.stateby_ad[ad] = set() - self.stateby_ad[ad].add(state_var) - - """ self.todo.add(s) - """ - if not ad in self.cpt: - self.cpt[ad] = 0 - """ - """ - def get_next_min(self): - state_by_ad = {} - for state in self.todo: - ad = state[1] - if not ad in state_by_ad: - state_by_ad[ad] = [] - state_by_ad[ad].append(state) - print "XX", [len(x) for x in state_by_ad.values()] - state_by_ad = state_by_ad.items() - state_by_ad.sort(key=lambda x:len(x[1])) - state_by_ad.reverse() - return state_by_ad.pop()[1][0] - """ - def get_next_state(self): state = self.todo.pop() return state @@ -273,16 +217,10 @@ class symb_exec_func: self.total_done += 1 print 'CPT', self.total_done while self.todo: - # if self.total_done>20: - # self.get_next_min() - # state = self.todo.pop() state = self.get_next_state() parent, ad, s = state self.states_done.add(state) self.states_var_done.add(state) - # if s in self.states_var_done: - # print "state done" - # continue sb = SymbolicExecutionEngine(self.ir_arch, dict(s)) diff --git a/miasm2/analysis/debugging.py b/miasm2/analysis/debugging.py index fc03eb17..6b88f00a 100644 --- a/miasm2/analysis/debugging.py +++ b/miasm2/analysis/debugging.py @@ -273,7 +273,7 @@ class DebugCmd(cmd.Cmd, object): def add_breakpoints(self, bp_addr): for addr in bp_addr: - addr = int(addr, 0) + addr = int(addr, 0) good = True for i, dbg_obj in enumerate(self.dbg.bp_list): diff --git a/miasm2/analysis/disasm_cb.py b/miasm2/analysis/disasm_cb.py index e759e313..0dc482ac 100644 --- a/miasm2/analysis/disasm_cb.py +++ b/miasm2/analysis/disasm_cb.py @@ -5,7 +5,6 @@ from miasm2.expression.simplifications import expr_simp from miasm2.core.asmblock \ import AsmSymbolPool, AsmConstraintNext, AsmConstraintTo from miasm2.core.utils import upck32 -# from miasm2.core.graph import DiGraph def get_ira(mnemo, attrib): @@ -32,11 +31,8 @@ def arm_guess_subcall( ir_arch.add_block(cur_bloc) ir_blocks = ir_arch.blocks.values() - # flow_graph = DiGraph() to_add = set() for irblock in ir_blocks: - # print 'X'*40 - # print irblock pc_val = None lr_val = None for exprs in irblock: @@ -53,17 +49,13 @@ def arm_guess_subcall( l = cur_bloc.lines[-1] if lr_val.arg != l.offset + l.l: continue - # print 'IS CALL!' l = symbol_pool.getby_offset_create(int(lr_val)) c = AsmConstraintNext(l) to_add.add(c) offsets_to_dis.add(int(lr_val)) - # if to_add: - # print 'R'*70 for c in to_add: - # print c cur_bloc.addto(c) @@ -80,16 +72,11 @@ def arm_guess_jump_table( ir_blocks = ir_arch.blocks.values() for irblock in ir_blocks: - # print 'X'*40 - # print irblock pc_val = None - # lr_val = None for exprs in irblock: for e in exprs: if e.dst == ir_arch.pc: pc_val = e.src - # if e.dst == mnemo.regs.LR: - # lr_val = e.src if pc_val is None: continue if not isinstance(pc_val, ExprMem): diff --git a/miasm2/analysis/sandbox.py b/miasm2/analysis/sandbox.py index e77b1669..b1147adb 100644 --- a/miasm2/analysis/sandbox.py +++ b/miasm2/analysis/sandbox.py @@ -57,16 +57,15 @@ class Sandbox(object): cls.__init__(self, **kwargs) # Logging options - if self.options.singlestep: - self.jitter.jit.log_mn = True - self.jitter.jit.log_regs = True + self.jitter.set_trace_log( + trace_instr=self.options.singlestep, + trace_regs=self.options.singlestep, + trace_new_blocks=self.options.dumpblocs + ) if not self.options.quiet_function_calls: log_func.setLevel(logging.INFO) - if self.options.dumpblocs: - self.jitter.jit.log_newbloc = True - @classmethod def parser(cls, *args, **kwargs): """ diff --git a/miasm2/arch/aarch64/jit.py b/miasm2/arch/aarch64/jit.py index 31570f52..b557a179 100644 --- a/miasm2/arch/aarch64/jit.py +++ b/miasm2/arch/aarch64/jit.py @@ -1,6 +1,6 @@ import logging -from miasm2.jitter.jitload import jitter, named_arguments +from miasm2.jitter.jitload import Jitter, named_arguments from miasm2.core import asmblock from miasm2.core.utils import pck64, upck64 from miasm2.arch.aarch64.sem import ir_aarch64b, ir_aarch64l @@ -11,12 +11,12 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s")) log.addHandler(hnd) log.setLevel(logging.CRITICAL) -class jitter_aarch64l(jitter): +class jitter_aarch64l(Jitter): max_reg_arg = 8 def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_aarch64l(sp), *args, **kwargs) + Jitter.__init__(self, ir_aarch64l(sp), *args, **kwargs) self.vm.set_little_endian() def push_uint64_t(self, value): @@ -69,7 +69,7 @@ class jitter_aarch64l(jitter): func_prepare_systemv = func_prepare_stdcall def init_run(self, *args, **kwargs): - jitter.init_run(self, *args, **kwargs) + Jitter.init_run(self, *args, **kwargs) self.cpu.PC = self.pc @@ -77,5 +77,5 @@ class jitter_aarch64b(jitter_aarch64l): def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_aarch64b(sp), *args, **kwargs) + Jitter.__init__(self, ir_aarch64b(sp), *args, **kwargs) self.vm.set_big_endian() diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index ad582878..c232e8dc 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -350,7 +350,36 @@ def csel(arg1, arg2, arg3, arg4): cond_expr = cond2expr[arg4.name] arg1 = arg2 if cond_expr else arg3 +def ccmp(ir, instr, arg1, arg2, arg3, arg4): + e = [] + if(arg2.is_int): + arg2=m2_expr.ExprInt(arg2.arg.arg,arg1.size) + default_nf = arg3[0:1] + default_zf = arg3[1:2] + default_cf = arg3[2:3] + default_of = arg3[3:4] + cond_expr = cond2expr[arg4.name] + res = arg1 - arg2 + new_nf = nf + new_zf = update_flag_zf(res)[0].src + new_cf = update_flag_sub_cf(arg1, arg2, res).src + new_of = update_flag_sub_of(arg1, arg2, res).src + + e.append(m2_expr.ExprAff(nf, m2_expr.ExprCond(cond_expr, + new_nf, + default_nf))) + e.append(m2_expr.ExprAff(zf, m2_expr.ExprCond(cond_expr, + new_zf, + default_zf))) + e.append(m2_expr.ExprAff(cf, m2_expr.ExprCond(cond_expr, + new_cf, + default_cf))) + e.append(m2_expr.ExprAff(of, m2_expr.ExprCond(cond_expr, + new_of, + default_of))) + return e, [] + def csinc(ir, instr, arg1, arg2, arg3, arg4): e = [] cond_expr = cond2expr[arg4.name] @@ -761,6 +790,7 @@ mnemo_func.update({ 'cmp': cmp, 'cmn': cmn, 'movk': movk, + 'ccmp': ccmp, 'csinc': csinc, 'csinv': csinv, 'csneg': csneg, diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index 17b57ba4..624642cf 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -1038,16 +1038,12 @@ class arm_op2(arm_arg): shift_kind = shift & 1 shift_type = (shift >> 1) & 3 shift >>= 3 - # print self.parent.immop.value, hex(shift), hex(shift_kind), - # hex(shift_type) if shift_kind: # shift kind is reg if shift & 1: - # log.debug('error in shift1') return False rs = shift >> 1 if rs == 0xf: - # log.debug('error in shift2') return False shift_op = regs_expr[rs] else: @@ -2155,12 +2151,10 @@ class armt_rlist_pclr(armt_rlist): reg_l = list(e.args) self.parent.pclr.value = 0 if self.parent.pp.value == 0: - # print 'push' if regs_expr[14] in reg_l: reg_l.remove(regs_expr[14]) self.parent.pclr.value = 1 else: - # print 'pop', if regs_expr[15] in reg_l: reg_l.remove(regs_expr[15]) self.parent.pclr.value = 1 diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py index b92e2c32..ef2e14ae 100644 --- a/miasm2/arch/arm/jit.py +++ b/miasm2/arch/arm/jit.py @@ -1,6 +1,6 @@ import logging -from miasm2.jitter.jitload import jitter, named_arguments +from miasm2.jitter.jitload import Jitter, named_arguments from miasm2.core import asmblock from miasm2.core.utils import pck32, upck32 from miasm2.arch.arm.sem import ir_armb, ir_arml, ir_armtl, ir_armtb, cond_dct_inv, tab_cond @@ -51,12 +51,12 @@ class arm_CGen(CGen): return irblocks_list -class jitter_arml(jitter): +class jitter_arml(Jitter): C_Gen = arm_CGen def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_arml(sp), *args, **kwargs) + Jitter.__init__(self, ir_arml(sp), *args, **kwargs) self.vm.set_little_endian() def push_uint32_t(self, value): @@ -107,7 +107,7 @@ class jitter_arml(jitter): get_arg_n_systemv = get_arg_n_stdcall def init_run(self, *args, **kwargs): - jitter.init_run(self, *args, **kwargs) + Jitter.init_run(self, *args, **kwargs) self.cpu.PC = self.pc @@ -116,7 +116,7 @@ class jitter_armb(jitter_arml): def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_armb(sp), *args, **kwargs) + Jitter.__init__(self, ir_armb(sp), *args, **kwargs) self.vm.set_big_endian() @@ -125,5 +125,5 @@ class jitter_armtl(jitter_arml): def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_armtl(sp), *args, **kwargs) + Jitter.__init__(self, ir_armtl(sp), *args, **kwargs) self.vm.set_little_endian() diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index c80e9826..ccd56e8f 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -635,7 +635,6 @@ def st_ld_r(ir, instr, a, a2, b, store=False, size=32, s_ext=False, z_ext=False) base, off = b.args[0], b.args[1] # ExprInt(size/8, 32) else: base, off = b, ExprInt(0, 32) - # print a, wb, base, off, postinc if postinc: ad = base else: @@ -734,13 +733,11 @@ def ldrsh(ir, instr, a, b): def st_ld_m(ir, instr, a, b, store=False, postinc=False, updown=False): e = [] wb = False - # sb = False dst = None if isinstance(a, ExprOp) and a.op == 'wback': wb = True a = a.args[0] if isinstance(b, ExprOp) and b.op == 'sbit': - # sb = True b = b.args[0] regs = b.args base = a diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index 180f8b0a..dad70de8 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -1,6 +1,6 @@ import logging -from miasm2.jitter.jitload import jitter, named_arguments +from miasm2.jitter.jitload import Jitter, named_arguments from miasm2.core import asmblock from miasm2.core.utils import pck32, upck32 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b @@ -80,13 +80,13 @@ class mipsCGen(CGen): return out -class jitter_mips32l(jitter): +class jitter_mips32l(Jitter): C_Gen = mipsCGen def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_mips32l(sp), *args, **kwargs) + Jitter.__init__(self, ir_mips32l(sp), *args, **kwargs) self.vm.set_little_endian() def push_uint32_t(self, value): @@ -102,7 +102,7 @@ class jitter_mips32l(jitter): return upck32(self.vm.get_mem(self.cpu.SP + 4 * index, 4)) def init_run(self, *args, **kwargs): - jitter.init_run(self, *args, **kwargs) + Jitter.init_run(self, *args, **kwargs) self.cpu.PC = self.pc # calling conventions @@ -146,5 +146,5 @@ class jitter_mips32b(jitter_mips32l): def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_mips32b(sp), *args, **kwargs) + Jitter.__init__(self, ir_mips32b(sp), *args, **kwargs) self.vm.set_big_endian() diff --git a/miasm2/arch/msp430/jit.py b/miasm2/arch/msp430/jit.py index dd5fe94e..dcd7e91a 100644 --- a/miasm2/arch/msp430/jit.py +++ b/miasm2/arch/msp430/jit.py @@ -1,4 +1,4 @@ -from miasm2.jitter.jitload import jitter +from miasm2.jitter.jitload import Jitter from miasm2.core import asmblock from miasm2.core.utils import pck16, upck16 from miasm2.arch.msp430.sem import ir_msp430 @@ -11,11 +11,11 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s")) log.addHandler(hnd) log.setLevel(logging.CRITICAL) -class jitter_msp430(jitter): +class jitter_msp430(Jitter): def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_msp430(sp), *args, **kwargs) + Jitter.__init__(self, ir_msp430(sp), *args, **kwargs) self.vm.set_little_endian() def push_uint16_t(self, value): @@ -37,6 +37,6 @@ class jitter_msp430(jitter): return value def init_run(self, *args, **kwargs): - jitter.init_run(self, *args, **kwargs) + Jitter.init_run(self, *args, **kwargs) self.cpu.PC = self.pc diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py index 877c2a70..a3521fb5 100644 --- a/miasm2/arch/msp430/sem.py +++ b/miasm2/arch/msp430/sem.py @@ -434,7 +434,6 @@ class ir_msp430(IntermediateRepresentation): pass def get_ir(self, instr): - # print instr#, args args = instr.args instr_ir, extra_ir = mnemo_func[instr.name](self, instr, *args) self.mod_sr(instr, instr_ir, extra_ir) diff --git a/miasm2/arch/ppc/jit.py b/miasm2/arch/ppc/jit.py index 9134e032..e79faabd 100644 --- a/miasm2/arch/ppc/jit.py +++ b/miasm2/arch/ppc/jit.py @@ -1,4 +1,4 @@ -from miasm2.jitter.jitload import jitter, named_arguments +from miasm2.jitter.jitload import Jitter, named_arguments from miasm2.core import asmblock from miasm2.arch.ppc.sem import ir_ppc32b import struct @@ -11,7 +11,7 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s")) log.addHandler(hnd) log.setLevel(logging.CRITICAL) -class jitter_ppc32b(jitter): +class jitter_ppc32b(Jitter): max_reg_arg = 8 def __init__(self, *args, **kwargs): @@ -66,5 +66,5 @@ class jitter_ppc32b(jitter): def init_run(self, *args, **kwargs): - jitter.init_run(self, *args, **kwargs) + Jitter.init_run(self, *args, **kwargs) self.cpu.PC = self.pc diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index a12a66f5..5485ed85 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -1,6 +1,6 @@ import logging -from miasm2.jitter.jitload import jitter, named_arguments +from miasm2.jitter.jitload import Jitter, named_arguments from miasm2.core import asmblock from miasm2.core.utils import pck16, pck32, pck64, upck16, upck32, upck64 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 @@ -34,13 +34,13 @@ class x86_64_CGen(x86_32_CGen): out.append('dump_gpregs_64(jitcpu->cpu);') return out -class jitter_x86_16(jitter): +class jitter_x86_16(Jitter): C_Gen = x86_32_CGen def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_x86_16(sp), *args, **kwargs) + Jitter.__init__(self, ir_x86_16(sp), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode @@ -62,17 +62,17 @@ class jitter_x86_16(jitter): return upck16(self.vm.get_mem(self.cpu.SP + 4 * index, 4)) def init_run(self, *args, **kwargs): - jitter.init_run(self, *args, **kwargs) + Jitter.init_run(self, *args, **kwargs) self.cpu.IP = self.pc -class jitter_x86_32(jitter): +class jitter_x86_32(Jitter): C_Gen = x86_32_CGen def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_x86_32(sp), *args, **kwargs) + Jitter.__init__(self, ir_x86_32(sp), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False @@ -104,7 +104,7 @@ class jitter_x86_32(jitter): return upck32(self.vm.get_mem(self.cpu.ESP + 4 * index, 4)) def init_run(self, *args, **kwargs): - jitter.init_run(self, *args, **kwargs) + Jitter.init_run(self, *args, **kwargs) self.cpu.EIP = self.pc # calling conventions @@ -180,7 +180,7 @@ class jitter_x86_32(jitter): -class jitter_x86_64(jitter): +class jitter_x86_64(Jitter): C_Gen = x86_64_CGen args_regs_systemv = ['RDI', 'RSI', 'RDX', 'RCX', 'R8', 'R9'] @@ -188,7 +188,7 @@ class jitter_x86_64(jitter): def __init__(self, *args, **kwargs): sp = asmblock.AsmSymbolPool() - jitter.__init__(self, ir_x86_64(sp), *args, **kwargs) + Jitter.__init__(self, ir_x86_64(sp), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False @@ -211,7 +211,7 @@ class jitter_x86_64(jitter): return upck64(self.vm.get_mem(self.cpu.RSP + 8 * index, 8)) def init_run(self, *args, **kwargs): - jitter.init_run(self, *args, **kwargs) + Jitter.init_run(self, *args, **kwargs) self.cpu.RIP = self.pc # calling conventions diff --git a/miasm2/core/asmblock.py b/miasm2/core/asmblock.py index 35b7e1db..08ff25e9 100644 --- a/miasm2/core/asmblock.py +++ b/miasm2/core/asmblock.py @@ -521,7 +521,7 @@ class AsmSymbolPool(object): return "".join("%s\n" % loc_key for loc_key in self._loc_keys) def __getitem__(self, item): - warnings.warn('DEPRECATION WARNING: use "offset_to_loc_key" or "name_to_loc_key"') + warnings.warn('DEPRECATION WARNING: use "getby_name" or "getby_offset"') if item in self._name_to_loc_key: return self._name_to_loc_key[item] if item in self._offset_to_loc_key: @@ -529,7 +529,7 @@ class AsmSymbolPool(object): raise KeyError('unknown symbol %r' % item) def __contains__(self, item): - warnings.warn('DEPRECATION WARNING: use "offset_to_loc_key" or "name_to_loc_key"') + warnings.warn('DEPRECATION WARNING: use "getby_name" or "getby_offset"') return item in self._name_to_loc_key or item in self._offset_to_loc_key def merge(self, symbol_pool): diff --git a/miasm2/core/cpu.py b/miasm2/core/cpu.py index a142ab77..80f81aff 100644 --- a/miasm2/core/cpu.py +++ b/miasm2/core/cpu.py @@ -1030,7 +1030,7 @@ class instruction(object): if name == '_': fixed_expr[exprloc] = self.get_asm_next_offset(exprloc) continue - if not name in symbols: + if symbols.getby_name(name) is None: raise ValueError('Unresolved symbol: %r' % exprloc) offset = symbols.loc_key_to_offset(loc_key) diff --git a/miasm2/core/parse_asm.py b/miasm2/core/parse_asm.py index 86871c37..3b97cbb6 100644 --- a/miasm2/core/parse_asm.py +++ b/miasm2/core/parse_asm.py @@ -73,30 +73,6 @@ def guess_next_new_label(symbol_pool): i += 1 -def replace_expr_labels(expr, symbol_pool, replace_id): - """Create LocKey of the expression @expr in the @symbol_pool - Update @replace_id""" - - if not expr.is_loc(): - return expr - - old_name = symbol_pool.loc_key_to_name(expr.loc_key) - new_lbl = symbol_pool.getby_name_create(old_name) - replace_id[expr] = ExprLoc(new_lbl, expr.size) - return replace_id[expr] - - -def replace_orphan_labels(instr, symbol_pool): - """Link orphan labels used by @instr to the @symbol_pool""" - - for i, arg in enumerate(instr.args): - replace_id = {} - arg.visit(lambda e: replace_expr_labels(e, - symbol_pool, - replace_id)) - instr.args[i] = instr.args[i].replace_expr(replace_id) - - STATE_NO_BLOC = 0 STATE_IN_BLOC = 1 @@ -224,8 +200,6 @@ def parse_txt(mnemo, attrib, txt, symbol_pool=None): line = line.strip(' ').strip('\t') instr = mnemo.fromstring(line, symbol_pool, attrib) - replace_orphan_labels(instr, symbol_pool) - if instr.dstflow(): instr.dstflow2label(symbol_pool) lines.append(instr) diff --git a/miasm2/expression/simplifications_common.py b/miasm2/expression/simplifications_common.py index 13b25ce2..149c5b8d 100644 --- a/miasm2/expression/simplifications_common.py +++ b/miasm2/expression/simplifications_common.py @@ -250,6 +250,26 @@ def simp_cst_propagation(e_s, expr): e_s(Y.msb()) == ExprInt(0, 1)): args = [args[0].args[0], X + Y] + # ((var >> int1) << int1) => var & mask + # ((var << int1) >> int1) => var & mask + if (op_name in ['<<', '>>'] and + args[0].is_op() and + args[0].op in ['<<', '>>'] and + op_name != args[0]): + var = args[0].args[0] + int1 = args[0].args[1] + int2 = args[1] + if int1 == int2 and int1.is_int() and int(int1) < expr.size: + if op_name == '>>': + mask = ExprInt((1 << (expr.size - int(int1))) - 1, expr.size) + else: + mask = ExprInt( + ((1 << int(int1)) - 1) ^ ((1 << expr.size) - 1), + expr.size + ) + ret = var & mask + return ret + # ((A & A.mask) if op_name == "&" and args[-1] == expr.mask: return ExprOp('&', *args[:-1]) diff --git a/miasm2/jitter/jitcore.py b/miasm2/jitter/jitcore.py index bf56b9de..9d36bb97 100644 --- a/miasm2/jitter/jitcore.py +++ b/miasm2/jitter/jitcore.py @@ -16,6 +16,7 @@ # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. # from hashlib import md5 +import warnings from miasm2.core.asmblock import disasmEngine, AsmBlockBad from miasm2.core.interval import interval @@ -52,7 +53,6 @@ class JitCore(object): self.addr2obj = {} self.addr2objref = {} self.blocs_mem_interval = interval() - self.disasm_cb = None self.split_dis = set() self.options = {"jit_maxline": 50, # Maximum number of line jitted "max_exec_per_call": 0 # 0 means no limit @@ -65,7 +65,6 @@ class JitCore(object): follow_call=False, dontdis_retcall=False, split_dis=self.split_dis, - dis_block_callback=self.disasm_cb ) @@ -145,7 +144,6 @@ class JitCore(object): # Prepare disassembler self.mdis.lines_wd = self.options["jit_maxline"] - self.mdis.dis_block_callback = self.disasm_cb # Disassemble it cur_block = self.mdis.dis_block(addr) @@ -295,3 +293,13 @@ class JitCore(object): self.log_regs, block_raw)).hexdigest() return block_hash + + @property + def disasm_cb(self): + warnings.warn("Deprecated API: use .mdis.dis_block_callback") + return self.mdis.dis_block_callback + + @disasm_cb.setter + def disasm_cb(self, value): + warnings.warn("Deprecated API: use .mdis.dis_block_callback") + self.mdis.dis_block_callback = value diff --git a/miasm2/jitter/jitload.py b/miasm2/jitter/jitload.py index 28200997..56ad4561 100644 --- a/miasm2/jitter/jitload.py +++ b/miasm2/jitter/jitload.py @@ -1,5 +1,6 @@ import logging +import warnings from functools import wraps from collections import Sequence, namedtuple, Iterator @@ -160,7 +161,7 @@ class ExceptionHandle(): return not self.__eq__(to_cmp) -class jitter(object): +class Jitter(object): "Main class for JIT handling" @@ -484,3 +485,33 @@ class jitter(object): self.symbexec.update_cpu_from_engine() return ret + + def set_trace_log(self, + trace_instr=True, trace_regs=True, + trace_new_blocks=False): + """ + Activate/Deactivate trace log options + + @trace_instr: activate instructions tracing log + @trace_regs: activate registers tracing log + @trace_new_blocks: dump new code blocks log + """ + + # As trace state changes, clear already jitted blocks + self.jit.clear_jitted_blocks() + + self.jit.log_mn = trace_instr + self.jit.log_regs = trace_regs + self.jit.log_newbloc = trace_new_blocks + + +class jitter(Jitter): + """ + DEPRECATED object + Use Jitter instead of jitter + """ + + + def __init__(self, *args, **kwargs): + warnings.warn("Deprecated API: use Jitter") + super(jitter, self).__init__(*args, **kwargs) diff --git a/miasm2/jitter/loader/elf.py b/miasm2/jitter/loader/elf.py index deaebd09..01dea647 100644 --- a/miasm2/jitter/loader/elf.py +++ b/miasm2/jitter/loader/elf.py @@ -32,7 +32,6 @@ def preload_elf(vm, e, runtime_lib, patch_vm_imp=True): # XXX quick hack fa = get_import_address_elf(e) dyn_funcs = {} - # log.debug('imported funcs: %s' % fa) for (libname, libfunc), ads in fa.items(): for ad in ads: ad_base_lib = runtime_lib.lib_get_add_base(libname) @@ -77,7 +76,6 @@ def vm_load_elf(vm, fdata, name="", **kargs): # -2: Trick to avoid merging 2 consecutive pages i += [(a_addr, b_addr - 2)] for a, b in i.intervals: - # print hex(a), hex(b) vm.add_memory_page(a, PAGE_READ | PAGE_WRITE, "\x00" * (b + 2 - a), repr(name)) diff --git a/test/analysis/data_flow.py b/test/analysis/data_flow.py index c3469109..d5b197d2 100644 --- a/test/analysis/data_flow.py +++ b/test/analysis/data_flow.py @@ -673,7 +673,6 @@ for test_nb, test in enumerate([(G1_IRA, G1_EXP_IRA), reaching_defs = ReachingDefinitions(g_ira) defuse = DiGraphDefUse(reaching_defs, deref_mem=True) - #open("defuse_%02d.dot" % (test_nb+1), "w").write(defuse.dot()) # # Simplify graph dead_simp(g_ira) diff --git a/test/analysis/depgraph.py b/test/analysis/depgraph.py index 4e023761..86857182 100644 --- a/test/analysis/depgraph.py +++ b/test/analysis/depgraph.py @@ -1058,7 +1058,7 @@ for test_nb, test in enumerate([(G1_IRA, G1_INPUT), all_results.add(unflatGraph(flatGraph(result.graph))) open("graph_test_%02d_%02d.dot" % (test_nb + 1, i), "w").write(dg2graph(result.graph)) - # print all_flat + if g_ind == 0: all_flat = sorted(all_flat) all_flats.append(all_flat) diff --git a/test/analysis/dse.py b/test/analysis/dse.py index 5a72db34..4367f6f7 100644 --- a/test/analysis/dse.py +++ b/test/analysis/dse.py @@ -34,8 +34,7 @@ class DSETest(object): self.myjit = jitter(jitter_engine) self.myjit.init_stack() - self.myjit.jit.log_regs = True - self.myjit.jit.log_mn = True + self.myjit.set_trace_log() self.dse = None self.assembly = None diff --git a/test/arch/aarch64/unit/asm_test.py b/test/arch/aarch64/unit/asm_test.py index ca27ef9d..437a8056 100644 --- a/test/arch/aarch64/unit/asm_test.py +++ b/test/arch/aarch64/unit/asm_test.py @@ -16,16 +16,11 @@ class Asm_Test(object): self.myjit = Machine("aarch64l").jitter(jitter) self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - - def __call__(self): self.asm() self.run() self.check() - def asm(self): blocks, symbol_pool = parse_asm.parse_txt(mn_aarch64, 'l', self.TXT, symbol_pool = self.myjit.ir_arch.symbol_pool) diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index 90d137d0..f69bb104 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -5,41 +5,6 @@ from pdb import pm symbol_pool = AsmSymbolPool() -if 0: - a = bs('00') - b = bs('01') - c = bs(l=2) - d = bs(l=4, fname='rd') - e = bs_name(l=1, name={'ADD': 0, 'SUB': 1}) - assert(isinstance(e, bs_divert)) - scc = bs_mod_name(l=1, mn_mod=['', 'S']) - f = bs(l=1, cls=(arm_reg,)) - - class arm_mov(mn_arm): - fields = [bs('0000'), bs('0000'), bs('0000')] - - class arm_DATA(mn_arm): - fields = [bs('1111'), e, scc, f, bs('0')] - mn = mn_arm.dis(0xF000000) - - -if 0: - import cProfile - cProfile.run('mn_arm.dis("\xe1\xa0\xa0\x06", "l")') - # l = mn_arm.dis(bin_stream("\xe1\xa0\xa0\x06"), mode_arm) - # print l - """ - mode = 64 - l = mn_x86.fromstring("ADC DWORD PTR [RAX], 0x11223344", mode) - print 'xx' - #t= time.time() - import cProfile - def f(): - x = l.asm(mode) - print x - cProfile.run('f()') - """ - def h2i(s): return s.replace(' ', '').decode('hex') @@ -268,15 +233,11 @@ for s, l in reg_tests_arm: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] l = mn_arm.fromstring(s, symbol_pool, 'l') - # print l assert(str(l) == s) a = mn_arm.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) reg_tests_armt = [ @@ -720,36 +681,14 @@ for s, l in reg_tests_armt: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] l = mn_armt.fromstring(s, symbol_pool, 'l') - # print l assert(str(l) == s) print 'Asm..', l a = mn_armt.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) -""" -print "*"*30, "START SPECIAL PARSING", "*"*30 -parse_tests = [ - "MOV LR, toto", - "MOV LR, 1+toto", - "MOV LR, (lend-lstart)^toto<<<R1", - "MOV LR, R1 LSL (l_end-l_start)^toto<<<R1", - "MOV LR, R1 LSL (l_end-l_start)^toto<<<R1", - "EOR R0, R1, toto^titi+1", - ] - -for l in parse_tests: - print "-"*80 - l = mn_arm.fromstring(l, 'l') - print l.name, ", ".join([str(a) for a in l.args]) -""" - - print 'TEST time', time.time() - ts # speed test arm @@ -787,7 +726,6 @@ instr_num = 0 ts = time.time() while off < bs.getlen(): mn = mn_armt.dis(bs, 'l', off) - # print instr_num, off, str(mn) instr_num += 1 off += mn.l print 'instr per sec:', instr_num / (time.time() - ts) diff --git a/test/arch/mips32/arch.py b/test/arch/mips32/arch.py index c6b68c0c..6fc36d13 100644 --- a/test/arch/mips32/arch.py +++ b/test/arch/mips32/arch.py @@ -228,13 +228,9 @@ for s, l in reg_tests_mips32: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] l = mn_mips32.fromstring(s, symbol_pool, 'b') - # print l assert(str(l) == s) a = mn_mips32.asm(l, 'b') print [x for x in a] print repr(b) - # print mn.args assert(b in a) diff --git a/test/arch/mips32/unit/asm_test.py b/test/arch/mips32/unit/asm_test.py index f03a32d7..a2203783 100644 --- a/test/arch/mips32/unit/asm_test.py +++ b/test/arch/mips32/unit/asm_test.py @@ -18,9 +18,6 @@ class Asm_Test(object): self.myjit = Machine("mips32l").jitter(jitter) self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - def __call__(self): self.asm() self.run() diff --git a/test/arch/msp430/arch.py b/test/arch/msp430/arch.py index 3df2becb..08e5bdae 100644 --- a/test/arch/msp430/arch.py +++ b/test/arch/msp430/arch.py @@ -95,13 +95,9 @@ for s, l in reg_tests_msp: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] l = mn_msp430.fromstring(s, symbol_pool, None) - # print l assert(str(l) == s) a = mn_msp430.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) diff --git a/test/arch/sh4/arch.py b/test/arch/sh4/arch.py index 574dcf49..9162fdbc 100644 --- a/test/arch/sh4/arch.py +++ b/test/arch/sh4/arch.py @@ -398,15 +398,11 @@ for s, l in reg_tests_sh4: print s print mn assert(str(mn) == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] l = mn_sh4.fromstring(s, symbol_pool, None) - # print l assert(str(l) == s) a = mn_sh4.asm(l) print [x for x in a] print repr(b) - # print mn.args assert(b in a) diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 05b31815..1865ceba 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -3062,17 +3062,13 @@ for mode, s, l, in reg_tests: print s print mn assert(str(mn).strip() == s) - # print hex(b) - # print [str(x.get()) for x in mn.args] print 'fromstring', repr(s) l = mn_x86.fromstring(s, symbol_pool, mode) - # print l print 'str args', [(str(x), x.size) for x in l.args] assert(str(l).strip(' ') == s) a = mn_x86.asm(l) print 'asm result', [x for x in a] print repr(b) - # test_file[mode[0]].write(b) for x in a: print "BYTES", repr(x) @@ -3086,7 +3082,6 @@ for mode, s, l, in reg_tests: assert(str(rl).strip(' ') == s) print repr(b), a assert(b in a) - # print mn.args print 'TEST time', time.time() - ts @@ -3118,9 +3113,7 @@ def profile_dis(o): print 'instr per sec:', instr_num / (time.time() - ts) import cProfile -# cProfile.run(r'mn_x86.dis("\x81\x54\x18\xfe\x44\x33\x22\x11", m32)') cProfile.run('profile_dis(o)') -# profile_dis(o) # Test instruction representation with prefix instr_bytes = '\x65\xc7\x00\x09\x00\x00\x00' diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py index 961967f9..4b802606 100644 --- a/test/arch/x86/unit/asm_test.py +++ b/test/arch/x86/unit/asm_test.py @@ -18,9 +18,6 @@ class Asm_Test(object): self.myjit = Machine(self.arch_name).jitter(jitter_engine) self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - def test_init(self): pass @@ -81,10 +78,6 @@ class Asm_Test_16(Asm_Test): self.myjit.stack_size = 0x1000 self.myjit.init_stack() - self.myjit.jit.log_regs = False - self.myjit.jit.log_mn = False - - def init_machine(self): self.myjit.vm.add_memory_page(self.run_addr, PAGE_READ | PAGE_WRITE, self.assembly) self.myjit.push_uint16_t(self.ret_addr) diff --git a/test/expression/simplifications.py b/test/expression/simplifications.py index a4e839cf..b2591a83 100644 --- a/test/expression/simplifications.py +++ b/test/expression/simplifications.py @@ -177,6 +177,10 @@ to_test = [(ExprInt(1, 32) - ExprInt(1, 32), ExprInt(0, 32)), (ExprInt(0x4142, 32)[:32], ExprInt(0x4142, 32)), (ExprInt(0x4142, 32)[:8], ExprInt(0x42, 8)), (ExprInt(0x4142, 32)[8:16], ExprInt(0x41, 8)), + (ExprOp('>>', ExprOp('<<', a, ExprInt(0x4, 32)), ExprInt(0x4, 32)), + ExprOp('&', a, ExprInt(0x0FFFFFFF, 32))), + (ExprOp('<<', ExprOp('>>', a, ExprInt(0x4, 32)), ExprInt(0x4, 32)), + ExprOp('&', a, ExprInt(0xFFFFFFF0, 32))), (a[:32], a), (a[:8][:8], a[:8]), (a[:16][:8], a[:8]), diff --git a/test/jitter/bad_block.py b/test/jitter/bad_block.py index 04c1f475..ae11e696 100644 --- a/test/jitter/bad_block.py +++ b/test/jitter/bad_block.py @@ -32,8 +32,7 @@ run_addr = 0x40000000 jitter.vm.add_memory_page(run_addr, PAGE_READ | PAGE_WRITE, data) -jitter.jit.log_regs = True -jitter.jit.log_mn = True +jitter.set_trace_log() jitter.push_uint32_t(0x1337beef) jitter.add_breakpoint(0x1337beef, code_sentinelle) diff --git a/test/jitter/jit_options.py b/test/jitter/jit_options.py index 4fe936d5..a0ddbc11 100644 --- a/test/jitter/jit_options.py +++ b/test/jitter/jit_options.py @@ -33,8 +33,7 @@ def init_jitter(): # Init jitter myjit.init_stack() - myjit.jit.log_regs = True - myjit.jit.log_mn = True + myjit.set_trace_log() myjit.push_uint32_t(0x1337beef) myjit.add_breakpoint(0x1337beef, code_sentinelle) diff --git a/test/jitter/jmp_out_mem.py b/test/jitter/jmp_out_mem.py index 49da16ad..93ae8304 100644 --- a/test/jitter/jmp_out_mem.py +++ b/test/jitter/jmp_out_mem.py @@ -35,8 +35,7 @@ run_addr = 0x40000000 jitter.vm.add_memory_page(run_addr, PAGE_READ | PAGE_WRITE, data) -jitter.jit.log_regs = True -jitter.jit.log_mn = True +jitter.set_trace_log() jitter.push_uint32_t(0x1337beef) jitter.add_breakpoint(0x1337beef, code_sentinelle) diff --git a/test/jitter/test_post_instr.py b/test/jitter/test_post_instr.py index edf86645..39e87616 100644 --- a/test/jitter/test_post_instr.py +++ b/test/jitter/test_post_instr.py @@ -23,8 +23,8 @@ jitter.vm.add_memory_page(0x1000, PAGE_READ|PAGE_WRITE, "\x00"*0x1000, "code pag # RET jitter.vm.set_mem(0x1000, "B844332211C3".decode('hex')) -jitter.jit.log_mn = True -jitter.jit.log_regs = True + +jitter.set_trace_log() def do_not_raise_me(jitter): raise ValueError("Should not be here") |