diff options
| -rw-r--r-- | miasm2/analysis/debugging.py | 2 | ||||
| -rw-r--r-- | miasm2/analysis/machine.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/mips32/arch.py | 3 | ||||
| -rw-r--r-- | miasm2/arch/mips32/ira.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/x86/arch.py | 18 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 9 | ||||
| -rw-r--r-- | miasm2/expression/simplifications_cond.py | 16 | ||||
| -rw-r--r-- | miasm2/ir/analysis.py | 2 |
8 files changed, 24 insertions, 32 deletions
diff --git a/miasm2/analysis/debugging.py b/miasm2/analysis/debugging.py index 61e2ed95..57f30181 100644 --- a/miasm2/analysis/debugging.py +++ b/miasm2/analysis/debugging.py @@ -77,7 +77,7 @@ class Debugguer(object): def init_memory_breakpoint(self): "Set exception handler on EXCEPT_BREAKPOINT_INTERN" - self.myjit.exception_handler + raise NotImplementedError("Not implemented") def add_memory_breakpoint(self, addr, size, read=False, write=False): "add mem bp @[addr, addr + size], on read/write/both" diff --git a/miasm2/analysis/machine.py b/miasm2/analysis/machine.py index d714dbb9..81ef4e9e 100644 --- a/miasm2/analysis/machine.py +++ b/miasm2/analysis/machine.py @@ -51,10 +51,8 @@ class Machine(object): mn = arch.mn_armt from miasm2.arch.arm.ira import ir_a_armtb as ira elif machine_name == "sh4": - from miasm2.arch.sh4.disasm import dis_sha4 as dis_engine from miasm2.arch.sh4 import arch mn = arch.mn_sh4 - from miasm2.arch.sh4.ira import ir_a_sh4 as ira elif machine_name == "x86_16": from miasm2.arch.x86.disasm import dis_x86_16 as dis_engine from miasm2.arch.x86 import arch, jit diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py index eb163daa..00dc09ed 100644 --- a/miasm2/arch/mips32/arch.py +++ b/miasm2/arch/mips32/arch.py @@ -486,8 +486,7 @@ class bs_cond(bs_mod_name): ] def modname(self, name, f_i): - fds - return name + self.args['mn_mod'][f_i] + raise NotImplementedError("Not implemented") class bs_cond_name(bs_divert): diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py index c070b4ba..f88172fb 100644 --- a/miasm2/arch/mips32/ira.py +++ b/miasm2/arch/mips32/ira.py @@ -49,8 +49,8 @@ class ir_a_mips32l(ir_mips32l, ira): #print 'TEST', l, hex(lr_val.arg), hex(l.offset + 8) #print lr_val.arg, hex(l.offset + l.l) if lr_val.arg != l.offset + 8: - fds - continue + raise ValueError("Wrong arg") + # print 'IS CALL!' lbl = bloc.get_next() new_lbl = self.gen_label() diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py index 2e858756..c5535153 100644 --- a/miasm2/arch/x86/arch.py +++ b/miasm2/arch/x86/arch.py @@ -2564,15 +2564,15 @@ class bs_cl1(bsi, m_arg): def sib_cond(cls, mode, v): - if admode_prefix((mode, v["opmode"], v["admode"])) == 16: - return None - if v['mod'] == 0b11: - return None - elif v['rm'] == 0b100: - return cls.ll - else: - return None - return v['rm'] == 0b100 + if admode_prefix((mode, v["opmode"], v["admode"])) == 16: + return None + if v['mod'] == 0b11: + return None + elif v['rm'] == 0b100: + return cls.ll + else: + return None + return v['rm'] == 0b100 class bs_cond_scale(bs_cond): diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 6e22e66d..bc98baf3 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -1845,18 +1845,15 @@ def ficom(ir, instr, a, b = None): def fcomi(ir, instr, a): - # Invalid emulation - InvalidEmulation + raise NotImplementedError("Invalid emulation") def fcomip(ir, instr, a): - # Invalid emulation - InvalidEmulation + raise NotImplementedError("Invalid emulation") def fucomi(ir, instr, a): - # Invalid emulation - InvalidEmulation + raise NotImplementedError("Invalid emulation") def fucomip(ir, instr, a, b): diff --git a/miasm2/expression/simplifications_cond.py b/miasm2/expression/simplifications_cond.py index e021ffc2..e6c890ab 100644 --- a/miasm2/expression/simplifications_cond.py +++ b/miasm2/expression/simplifications_cond.py @@ -146,14 +146,14 @@ def expr_simp_inverse(expr_simp, e): # Check for 2 symetric cases if r is False: - to_match = (ExprOp_inf_signed(jok1, jok2) ^ jok_small) - r = __MatchExprWrap(e, - to_match, - [jok1, jok2, jok_small]) - - if r is False: - return e - cur_sig = TOK_INF_SIGNED + to_match = (ExprOp_inf_signed(jok1, jok2) ^ jok_small) + r = __MatchExprWrap(e, + to_match, + [jok1, jok2, jok_small]) + + if r is False: + return e + cur_sig = TOK_INF_SIGNED else: cur_sig = TOK_INF_UNSIGNED diff --git a/miasm2/ir/analysis.py b/miasm2/ir/analysis.py index 037d1f4b..202f7631 100644 --- a/miasm2/ir/analysis.py +++ b/miasm2/ir/analysis.py @@ -322,8 +322,6 @@ class ira: eqs.append(ExprAff(n_w, v)) print '*' * 40 print irb - for eq in eqs: - eq irb.irs = [eqs] irb.lines = [None] |