diff options
| -rw-r--r-- | .travis.yml | 17 | ||||
| -rw-r--r-- | README.md | 2 | ||||
| -rw-r--r-- | example/disasm/full.py | 15 | ||||
| -rw-r--r-- | miasm2/arch/arm/arch.py | 12 | ||||
| -rw-r--r-- | miasm2/arch/arm/sem.py | 26 | ||||
| -rw-r--r-- | miasm2/arch/mep/jit.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/msp430/ira.py | 12 | ||||
| -rw-r--r-- | miasm2/arch/msp430/sem.py | 252 | ||||
| -rw-r--r-- | miasm2/arch/x86/arch.py | 5 | ||||
| -rw-r--r-- | miasm2/arch/x86/jit.py | 8 | ||||
| -rw-r--r-- | miasm2/core/asmbloc.py | 10 | ||||
| -rw-r--r-- | miasm2/core/bin_stream_ida.py | 6 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_aarch64.c | 8 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_arm.c | 9 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_mep.c | 9 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_msp430.c | 7 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_ppc32.c | 7 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_x86.c | 28 | ||||
| -rw-r--r-- | miasm2/jitter/codegen.py | 10 | ||||
| -rw-r--r-- | miasm2/jitter/jitcore_python.py | 2 | ||||
| -rw-r--r-- | miasm2/jitter/llvmconvert.py | 16 | ||||
| -rw-r--r-- | miasm2/jitter/vm_mngr_py.c | 4 | ||||
| -rw-r--r-- | test/arch/arm/arch.py | 12 | ||||
| -rwxr-xr-x | test/test_all.py | 5 |
24 files changed, 335 insertions, 151 deletions
diff --git a/.travis.yml b/.travis.yml index 60c4defd..f5c55368 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,7 +8,20 @@ addons: - llvm-6.0 - llvm-6.0-dev - g++-5 -env: CXX=g++-5 LLVM_CONFIG=llvm-config-6.0 +env: + global: CXX=g++-5 LLVM_CONFIG=llvm-config-6.0 + matrix: + - MIASM_TEST_EXTRA_ARG="-o regression -t long,python,llvm,gcc,z3,qemu,cparser" + - MIASM_TEST_EXTRA_ARG="-o example -t long,python,llvm,gcc,z3,qemu,cparser" + - MIASM_TEST_EXTRA_ARG="-o long" + - MIASM_TEST_EXTRA_ARG="-o qemu -t llvm,gcc" + - MIASM_TEST_EXTRA_ARG="-o qemu -t python,gcc" + - MIASM_TEST_EXTRA_ARG="-o qemu -t python,llvm" + - MIASM_TEST_EXTRA_ARG="-o llvm -t qemu,long" + - MIASM_TEST_EXTRA_ARG="-o gcc -t qemu,long" + - MIASM_TEST_EXTRA_ARG="-o python -t qemu,long" + - MIASM_TEST_EXTRA_ARG="-o z3" + - MIASM_TEST_EXTRA_ARG="-o cparser" before_script: - pip install -r optional_requirements.txt # codespell @@ -18,4 +31,4 @@ before_script: # install - python setup.py build build_ext - python setup.py install -script: cd test && python test_all.py && git ls-files -o --exclude-standard +script: cd test && python test_all.py $MIASM_TEST_EXTRA_ARG && git ls-files -o --exclude-standard diff --git a/README.md b/README.md index 5ac830d5..e8e257c8 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ [](https://travis-ci.org/cea-sec/miasm) -[](https://ci.appveyor.com/project/serpilliere/miasm-6lfba/branch/master) +[](https://ci.appveyor.com/project/cea-sec/miasm) [](https://codeclimate.com/github/cea-sec/miasm) [](https://gitter.im/cea-sec/miasm?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge) Reverse engineering framework in Python diff --git a/example/disasm/full.py b/example/disasm/full.py index 7f4d4945..4da32f67 100644 --- a/example/disasm/full.py +++ b/example/disasm/full.py @@ -261,7 +261,7 @@ if args.gen_ir: ssa = SSADiGraph(ircfg_a) ssa.transform(head) - open("ssa.dot", "wb").write(ssa.graph.dot()) + open("ssa.dot", "wb").write(ircfg_a.dot()) @@ -345,11 +345,11 @@ if args.propagexpr: ssa_forbidden_regs.update(ssa_regs) if args.verbose > 3: - open("ssa_%d.dot" % index, "wb").write(ssa.graph.dot()) + open("ssa_%d.dot" % index, "wb").write(ircfg_a.dot()) ir_arch_a.ssa_var.update(ssa._ssa_variable_to_expr) if args.verbose > 3: - open("ssa_orig.dot", "wb").write(ssa.graph.dot()) + open("ssa_orig.dot", "wb").write(ircfg_a.dot()) while modified: log.debug('Loop %d', index) @@ -396,10 +396,9 @@ if args.propagexpr: print '*'*80, "Remove phi" ssa._ssa_variable_to_expr = all_ssa_vars if args.verbose > 3: - open('final_ssa.dot', 'w').write(ssa.graph.dot()) + open('final_ssa.dot', 'w').write(ircfg_a.dot()) remove_phi(ssa, head) if args.verbose > 3: - open('final_no_phi.dot', 'w').write(ssa.graph.dot()) - dead_simp(ir_arch_a, ssa.graph) - open('final.dot', 'w').write(ssa.graph.dot()) - + open('final_no_phi.dot', 'w').write(ircfg_a.dot()) + dead_simp(ir_arch_a, ircfg_a) + open('final.dot', 'w').write(ircfg_a.dot()) diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index d4b7d05a..b08d7940 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -2378,13 +2378,17 @@ armtop("svc", [bs('11011111'), imm8]) armtop("b", [bs('11100'), offs11]) armtop("und", [bs('1101'), bs('1110'), imm8_d1]) -armtop("rev", [bs('10111010'), bs('00'), rsl, rdl], [rdl, rsl]) +armtop("rev", [bs('10111010'), bs('00'), rsl, rdl], [rdl, rsl]) +armtop("rev16", [bs('10111010'), bs('01'), rsl, rdl], [rdl, rsl]) armtop("uxtb", [bs('10110010'), bs('11'), rml, rdl], [rdl, rml]) armtop("uxth", [bs('10110010'), bs('10'), rml, rdl], [rdl, rml]) armtop("sxtb", [bs('10110010'), bs('01'), rml, rdl], [rdl, rml]) armtop("sxth", [bs('10110010'), bs('00'), rml, rdl], [rdl, rml]) +armtop("uxtab", [bs('111110100'), bs('101'), rn_nopc, bs('1111'), rd, bs('10'), rot2, rm_rot2], [rd, rn_nopc, rm_rot2]) +armtop("uxtah", [bs('111110100'), bs('001'), rn_nopc, bs('1111'), rd, bs('10'), rot2, rm_rot2], [rd, rn_nopc, rm_rot2]) + # thumb2 ###################### # # ARM Architecture Reference Manual Thumb-2 Supplement @@ -2768,6 +2772,7 @@ imm5_2 = bs(l=2, fname="imm5_2") imm_stype = bs(l=2, fname="stype") imm_stype_00 = bs('00', fname="stype") +imm_stype_01 = bs('01', fname="stype") imm_stype_11 = bs('11', fname="stype") @@ -3207,6 +3212,7 @@ armtop("rsb", [bs('11101011110'), scc, rn, bs('0'), imm5_3, rd, imm5_2, imm_styp armtop("orn", [bs('11101010011'), scc, rn_nopc, bs('0'), imm5_3, rd, imm5_2, imm_stype, rm_sh], [rd, rn_nopc, rm_sh] ) # lsl armtop("mov", [bs('11101010010'), scc, bs('1111'), bs('0'), imm5_3, rd_nosppc, imm5_2, imm_stype_00, rm_sh], [rd_nosppc, rm_sh] ) +armtop("mov", [bs('11101010010'), scc, bs('1111'), bs('0'), imm5_3, rd_nosppc, imm5_2, imm_stype_01, rm_sh], [rd_nosppc, rm_sh] ) armtop("mov", [bs('11101010010'), scc, bs('1111'), bs('0'), imm5_3, rd_nosppc, imm5_2, imm_stype_11, rm_sh], [rd_nosppc, rm_sh] ) @@ -3219,6 +3225,8 @@ armtop("eor", [bs('11110'), imm12_1, bs('00100'), scc, rn, bs('0'), imm12_3, rd_ armtop("add", [bs('11110'), imm12_1, bs('10000'), scc, rn_nosppc, bs('0'), imm12_3, rd, imm12_8_t4], [rd, rn_nosppc, imm12_8_t4]) armtop("cmp", [bs('11110'), imm12_1, bs('01101'), bs('1'), rn, bs('0'), imm12_3, bs('1111'), imm12_8] ) +armtop("cmp", [bs('11101011101'), bs('1'), rn, bs('0'), imm5_3, bs('1111'), imm5_2, imm_stype, rm_sh], [rn, rm_sh] ) + armtop("mvn", [bs('11110'), imm12_1, bs('00011'), scc, bs('1111'), bs('0'), imm12_3, rd, imm12_8]) armtop("rsb", [bs('11110'), imm12_1, bs('01110'), scc, rn_nosppc, bs('0'), imm12_3, rd, imm12_8], [rd, rn_nosppc, imm12_8]) @@ -3277,3 +3285,5 @@ armtop("clz", [bs('111110101011'), rm, bs('1111'), rd, bs('1000'), rm_cp], [rd, armtop("tbb", [bs('111010001101'), rn_noarg, bs('11110000000'), bs('0'), bs_deref_reg_reg], [bs_deref_reg_reg]) armtop("tbh", [bs('111010001101'), rn_noarg, bs('11110000000'), bs('1'), bs_deref_reg_reg_lsl_1], [bs_deref_reg_reg_lsl_1]) armtop("dsb", [bs('111100111011'), bs('1111'), bs('1000'), bs('1111'), bs('0100'), barrier_option]) + +armtop("adr", [bs('11110'), imm12_1, bs('100000'), bs('1111'), bs('0'), imm12_3, rd, imm12_8_t4], [rd, imm12_8_t4]) diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index 4af177d2..b5ab60d0 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -1089,7 +1089,7 @@ def cbnz(ir, instr, a, b): e = [] loc_next = ir.get_next_loc_key(instr) loc_next_expr = ExprLoc(loc_next, 32) - e.append(ir.IRDst, ExprCond(a, b, loc_next_expr)) + e.append(ExprAssign(ir.IRDst, ExprCond(a, b, loc_next_expr))) return e, [] @@ -1190,6 +1190,12 @@ def uxtab(ir, instr, a, b, c): return e, [] +def uxtah(ir, instr, a, b, c): + e = [] + e.append(ExprAssign(a, b + (c & ExprInt(0xffff, 32)))) + return e, [] + + def bkpt(ir, instr, a): e = [] e.append(ExprAssign(exception_flags, ExprInt(EXCEPT_SOFT_BP, 32))) @@ -1294,6 +1300,13 @@ def rev(ir, instr, a, b): return e, [] +def rev16(ir, instr, a, b): + e = [] + result = ExprCompose(b[8:16], b[:8], b[24:32], b[16:24]) + e.append(ExprAssign(a, result)) + return e, [] + + def nop(ir, instr): e = [] return e, [] @@ -1328,6 +1341,10 @@ def wfi(ir, instr): e = [] return e, [] +def adr(ir, instr, arg1, arg2): + e = [] + e.append(ExprAssign(arg1, (PC & ExprInt(0xfffffffc, 32)) + arg2)) + return e, [] COND_EQ = 0 COND_NE = 1 @@ -1494,8 +1511,10 @@ mnemo_condm0 = {'add': add, 'ubfx': ubfx, 'bfc': bfc, 'rev': rev, + 'rev16': rev16, 'clz': clz, 'uxtab': uxtab, + 'uxtah': uxtah, 'bkpt': bkpt, 'smulbb': smul, 'smulbt': smul, @@ -1579,6 +1598,7 @@ mnemo_nocond = {'lsr': lsr, 'cpsid': cpsid, 'wfe': wfe, 'wfi': wfi, + 'adr': adr, 'orn': orn, 'smlabb': smlabb, 'smlabt': smlabt, @@ -1706,7 +1726,7 @@ class ir_arml(IntermediateRepresentation): # Gen dummy irblock for IT instr loc_next = self.get_next_loc_key(instr) - dst = ExprAssign(self.IRDst, ExprId(loc_next, 32)) + dst = ExprAssign(self.IRDst, ExprLoc(loc_next, 32)) dst_blk = AssignBlock([dst], instr) assignments.append(dst_blk) irblock = IRBlock(loc, assignments) @@ -1743,7 +1763,7 @@ class ir_arml(IntermediateRepresentation): if split: raise NotImplementedError("Unsupported instr in IT block (%s)" % instr) - dst = ExprAssign(self.IRDst, ExprId(loc_next, 32)) + dst = ExprAssign(self.IRDst, ExprLoc(loc_next, 32)) dst_blk = AssignBlock([dst], instr) assignments.append(dst_blk) irblock = IRBlock(loc, assignments) diff --git a/miasm2/arch/mep/jit.py b/miasm2/arch/mep/jit.py index 913d508f..6c0e6ff5 100644 --- a/miasm2/arch/mep/jit.py +++ b/miasm2/arch/mep/jit.py @@ -43,11 +43,11 @@ class mep_CGen(CGen): return out - def gen_post_code(self, attrib): + def gen_post_code(self, attrib, pc_value): """Generate C code inserted after the current bloc""" # Call the base class method - out = super(mep_CGen, self).gen_post_code(attrib) + out = super(mep_CGen, self).gen_post_code(attrib, pc_value) # Implement the *REPEAT instructions logics tmp = r""" diff --git a/miasm2/arch/msp430/ira.py b/miasm2/arch/msp430/ira.py index 2a850d82..5b19956e 100644 --- a/miasm2/arch/msp430/ira.py +++ b/miasm2/arch/msp430/ira.py @@ -2,7 +2,8 @@ from miasm2.ir.analysis import ira from miasm2.arch.msp430.sem import ir_msp430 - +from miasm2.ir.ir import AssignBlock +from miasm2.expression.expression import * class ir_a_msp430_base(ir_msp430, ira): @@ -10,6 +11,15 @@ class ir_a_msp430_base(ir_msp430, ira): ir_msp430.__init__(self, loc_db) self.ret_reg = self.arch.regs.R15 + def call_effects(self, addr, instr): + call_assignblk = AssignBlock( + [ + ExprAssign(self.ret_reg, ExprOp('call_func_ret', addr, self.sp, self.arch.regs.R15)), + ExprAssign(self.sp, ExprOp('call_func_stack', addr, self.sp)) + ], + instr + ) + return [call_assignblk], [] class ir_a_msp430(ir_a_msp430_base): diff --git a/miasm2/arch/msp430/sem.py b/miasm2/arch/msp430/sem.py index 4736a51c..e0110d24 100644 --- a/miasm2/arch/msp430/sem.py +++ b/miasm2/arch/msp430/sem.py @@ -27,45 +27,67 @@ def reset_sr_res(): return [ExprAssign(res, ExprInt(0, 7))] -def update_flag_zf(a): - return [ExprAssign(zf, ExprCond(a, ExprInt(0, zf.size), ExprInt(1, zf.size)))] +def update_flag_cf_inv_zf(a): + return [ExprAssign(cf, ExprCond(a, ExprInt(1, 1), ExprInt(0, 1)))] -def update_flag_nf(a): - return [ExprAssign(nf, a.msb())] +def update_flag_zf_eq(a, b): + return [ExprAssign(zf, ExprOp("FLAG_EQ_CMP", a, b))] -def update_flag_pf(a): - return [ExprAssign(pf, ExprOp('parity', a & ExprInt(0xFF, a.size)))] +def update_flag_zf(a): + return [ExprAssign(zf, ExprOp("FLAG_EQ", a))] -def update_flag_cf_inv_zf(a): - return [ExprAssign(cf, ExprCond(a, ExprInt(1, cf.size), ExprInt(0, cf.size)))] +def update_flag_nf(arg): + return [ + ExprAssign( + nf, + ExprOp("FLAG_SIGN_SUB", arg, ExprInt(0, arg.size)) + ) + ] -def update_flag_zn_r(a): - e = [] - e += update_flag_zf(a) - e += update_flag_nf(a) - e += reset_sr_res() - return e +def update_flag_add_cf(op1, op2, res): + "Compute cf in @res = @op1 + @op2" + return [ExprAssign(cf, ExprOp("FLAG_ADD_CF", op1, op2))] -def update_flag_sub_cf(a, b, c): - return [ExprAssign(cf, - ((((a ^ b) ^ c) ^ ((a ^ c) & (a ^ b))).msb()) ^ ExprInt(1, 1))] +def update_flag_add_of(op1, op2, res): + "Compute of in @res = @op1 + @op2" + return [ExprAssign(of, ExprOp("FLAG_ADD_OF", op1, op2))] -def update_flag_add_cf(a, b, c): - return [ExprAssign(cf, (((a ^ b) ^ c) ^ ((a ^ c) & (~(a ^ b)))).msb())] +# checked: ok for sbb add because b & c before +cf +def update_flag_sub_cf(op1, op2, res): + "Compote CF in @op1 - @op2" + return [ExprAssign(cf, ExprOp("FLAG_SUB_CF", op1, op2) ^ ExprInt(1, 1))] -def update_flag_add_of(a, b, c): - return [ExprAssign(of, (((a ^ c) & (~(a ^ b)))).msb())] +def update_flag_sub_of(op1, op2, res): + "Compote OF in @res = @op1 - @op2" + return [ExprAssign(of, ExprOp("FLAG_SUB_OF", op1, op2))] -def update_flag_sub_of(a, b, c): - return [ExprAssign(of, (((a ^ c) & (a ^ b))).msb())] +def update_flag_arith_sub_zn(arg1, arg2): + """ + Compute znp flags for (arg1 - arg2) + """ + e = [] + e += update_flag_zf_eq(arg1, arg2) + e += [ExprAssign(nf, ExprOp("FLAG_SIGN_SUB", arg1, arg2))] + return e + + +def update_flag_arith_add_zn(arg1, arg2): + """ + Compute zf and nf flags for (arg1 + arg2) + """ + e = [] + e += update_flag_zf_eq(arg1, -arg2) + e += [ExprAssign(nf, ExprOp("FLAG_SIGN_SUB", arg1, -arg2))] + return e + def mng_autoinc(a, b, size): @@ -103,22 +125,31 @@ def mov_w(ir, instr, a, b): def and_b(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 8) - c = a[:8] & b[:8] - e.append(ExprAssign(b, c.zeroExtend(16))) - e += update_flag_zn_r(c) - e += update_flag_cf_inv_zf(c) + e, arg1, arg2 = mng_autoinc(a, b, 8) + arg1, arg2 = arg1[:8], arg2[:8] + res = arg1 & arg2 + e.append(ExprAssign(b, res.zeroExtend(16))) + + e += [ExprAssign(zf, ExprOp('FLAG_EQ_AND', arg1, arg2))] + e += [ExprAssign(nf, ExprOp("FLAG_SIGN_SUB", res, ExprInt(0, res.size)))] + e += reset_sr_res() + e += update_flag_cf_inv_zf(res) e += [ExprAssign(of, ExprInt(0, 1))] + return e, [] def and_w(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 16) - c = a & b - e.append(ExprAssign(b, c)) - e += update_flag_zn_r(c) - e += update_flag_cf_inv_zf(c) + e, arg1, arg2 = mng_autoinc(a, b, 16) + res = arg1 & arg2 + e.append(ExprAssign(arg2, res)) + + e += [ExprAssign(zf, ExprOp('FLAG_EQ_AND', arg1, arg2))] + e += [ExprAssign(nf, ExprOp("FLAG_SIGN_SUB", res, ExprInt(0, res.size)))] + e += reset_sr_res() + e += update_flag_cf_inv_zf(res) e += [ExprAssign(of, ExprInt(0, 1))] + return e, [] @@ -132,6 +163,12 @@ def bic_b(ir, instr, a, b): def bic_w(ir, instr, a, b): e, a, b = mng_autoinc(a, b, 16) + if b == SR: + # Special case + if a.is_int(1): + # cf + e.append(ExprAssign(cf, ExprInt(0, 1))) + return e, [] c = (a ^ ExprInt(0xffff, 16)) & b e.append(ExprAssign(b, c)) return e, [] @@ -145,30 +182,29 @@ def bis_w(ir, instr, a, b): def bit_w(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 16) - c = a & b - e += update_flag_zn_r(c) - e += update_flag_cf_inv_zf(c) - e.append(ExprAssign(of, ExprInt(0, 1))) - return e, [] + e, arg1, arg2 = mng_autoinc(a, b, 16) + res = arg1 & arg2 -""" -def sub_b(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 8) - c = b - a - e.append(ExprAssign(b, c)) - e += update_flag_zn_r(c) - e += update_flag_sub_cf(b, a, c) - return None, e, [] -""" + e += [ExprAssign(zf, ExprOp('FLAG_EQ_AND', arg1, arg2))] + e += [ExprAssign(nf, ExprOp("FLAG_SIGN_SUB", res, ExprInt(0, res.size)))] + e += reset_sr_res() + e += update_flag_cf_inv_zf(res) + e += [ExprAssign(of, ExprInt(0, 1))] + + return e, [] def sub_w(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 16) - c = b - a - e.append(ExprAssign(b, c)) - e += update_flag_zn_r(c) - e += update_flag_sub_cf(b, a, c) + e, arg1, arg2 = mng_autoinc(a, b, 16) + res = arg2 - arg1 + + e.append(ExprAssign(b, res)) + + e += update_flag_arith_sub_zn(arg2, arg1) + e += update_flag_sub_cf(arg2, arg1, res) + e += update_flag_sub_of(arg2, arg1, res) + e += reset_sr_res() + # micrcorruption # e += update_flag_sub_of(a, b, c) # e += update_flag_sub_of(b, a, c) @@ -176,27 +212,33 @@ def sub_w(ir, instr, a, b): def add_b(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 8) - if isinstance(b, ExprMem): - b = ExprMem(b.arg, 8) + e, arg1, arg2 = mng_autoinc(a, b, 8) + if isinstance(arg2, ExprMem): + arg2 = ExprMem(arg2.arg, 8) else: - b = b[:8] - a = a[:8] - c = b + a - e.append(ExprAssign(b, c)) - e += update_flag_zn_r(c) - e += update_flag_add_cf(a, b, c) - e += update_flag_add_of(a, b, c) + arg2 = arg2[:8] + arg1 = arg1[:8] + res = arg2 + arg1 + e.append(ExprAssign(b, res)) + + e += update_flag_arith_add_zn(arg2, arg1) + e += update_flag_add_cf(arg2, arg1, res) + e += update_flag_add_of(arg2, arg1, res) + e += reset_sr_res() + return e, [] def add_w(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 16) - c = b + a - e.append(ExprAssign(b, c)) - e += update_flag_zn_r(c) - e += update_flag_add_cf(a, b, c) - e += update_flag_add_of(a, b, c) + e, arg1, arg2 = mng_autoinc(a, b, 16) + res = arg2 + arg1 + e.append(ExprAssign(b, res)) + + e += update_flag_arith_add_zn(arg2, arg1) + e += update_flag_add_cf(arg2, arg1, res) + e += update_flag_add_of(arg2, arg1, res) + e += reset_sr_res() + return e, [] @@ -206,7 +248,6 @@ def dadd_w(ir, instr, a, b): c = ExprOp("bcdadd", b, a) # +zeroExtend(cf, 16)) e.append(ExprAssign(b, c)) - # e += update_flag_zn_r(c) # micrcorruption e += update_flag_zf(a) @@ -220,12 +261,16 @@ def dadd_w(ir, instr, a, b): def xor_w(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 16) - c = b ^ a - e.append(ExprAssign(b, c)) - e += update_flag_zn_r(c) + e, arg1, arg2 = mng_autoinc(a, b, 16) + res = arg2 ^ arg1 + e.append(ExprAssign(b, res)) + + e += [ExprAssign(zf, ExprOp('FLAG_EQ_CMP', arg2, arg1))] + e += update_flag_nf(res) + e += reset_sr_res() e += update_flag_cf_inv_zf(c) - e.append(ExprAssign(of, b.msb() & a.msb())) + e.append(ExprAssign(of, arg2.msb() & arg1.msb())) + return e, [] @@ -257,20 +302,27 @@ def swpb(ir, instr, a): def cmp_w(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 16) - c = b - a - e += update_flag_zn_r(c) - e += update_flag_sub_cf(b, a, c) - e += update_flag_sub_of(b, a, c) + e, arg1, arg2 = mng_autoinc(a, b, 16) + res = arg2 - arg1 + + e += update_flag_arith_sub_zn(arg2, arg1) + e += update_flag_sub_cf(arg2, arg1, res) + e += update_flag_sub_of(arg2, arg1, res) + e += reset_sr_res() + return e, [] def cmp_b(ir, instr, a, b): - e, a, b = mng_autoinc(a, b, 8) - c = b[:8] - a[:8] - e += update_flag_zn_r(c) - e += update_flag_sub_cf(b[:8], a[:8], c) - e += update_flag_sub_of(b[:8], a[:8], c) + e, arg1, arg2 = mng_autoinc(a, b, 8) + arg1, arg2 = arg1[:8], arg2[:8] + res = arg2 - arg1 + + e += update_flag_arith_sub_zn(arg2, arg1) + e += update_flag_sub_cf(arg2, arg1, res) + e += update_flag_sub_of(arg2, arg1, res) + e += reset_sr_res() + return e, [] @@ -278,8 +330,8 @@ def jz(ir, instr, a): loc_next = ir.get_next_loc_key(instr) loc_next_expr = ExprLoc(loc_next, 16) e = [] - e.append(ExprAssign(PC, ExprCond(zf, a, loc_next_expr))) - e.append(ExprAssign(ir.IRDst, ExprCond(zf, a, loc_next_expr))) + e.append(ExprAssign(PC, ExprCond(ExprOp("CC_EQ", zf), a, loc_next_expr))) + e.append(ExprAssign(ir.IRDst, ExprCond(ExprOp("CC_EQ", zf), a, loc_next_expr))) return e, [] @@ -287,8 +339,8 @@ def jnz(ir, instr, a): loc_next = ir.get_next_loc_key(instr) loc_next_expr = ExprLoc(loc_next, 16) e = [] - e.append(ExprAssign(PC, ExprCond(zf, loc_next_expr, a))) - e.append(ExprAssign(ir.IRDst, ExprCond(zf, loc_next_expr, a))) + e.append(ExprAssign(PC, ExprCond(ExprOp("CC_EQ", zf), loc_next_expr, a))) + e.append(ExprAssign(ir.IRDst, ExprCond(ExprOp("CC_EQ", zf), loc_next_expr, a))) return e, [] @@ -296,8 +348,8 @@ def jl(ir, instr, a): loc_next = ir.get_next_loc_key(instr) loc_next_expr = ExprLoc(loc_next, 16) e = [] - e.append(ExprAssign(PC, ExprCond(nf ^ of, a, loc_next_expr))) - e.append(ExprAssign(ir.IRDst, ExprCond(nf ^ of, a, loc_next_expr))) + e.append(ExprAssign(PC, ExprCond(ExprOp("CC_S<", nf, of), a, loc_next_expr))) + e.append(ExprAssign(ir.IRDst, ExprCond(ExprOp("CC_S<", nf, of), a, loc_next_expr))) return e, [] @@ -305,8 +357,8 @@ def jc(ir, instr, a): loc_next = ir.get_next_loc_key(instr) loc_next_expr = ExprLoc(loc_next, 16) e = [] - e.append(ExprAssign(PC, ExprCond(cf, a, loc_next_expr))) - e.append(ExprAssign(ir.IRDst, ExprCond(cf, a, loc_next_expr))) + e.append(ExprAssign(PC, ExprCond(ExprOp("CC_U>=", cf ^ ExprInt(1, 1)), a, loc_next_expr))) + e.append(ExprAssign(ir.IRDst, ExprCond(ExprOp("CC_U>=", cf ^ ExprInt(1, 1)), a, loc_next_expr))) return e, [] @@ -314,8 +366,8 @@ def jnc(ir, instr, a): loc_next = ir.get_next_loc_key(instr) loc_next_expr = ExprLoc(loc_next, 16) e = [] - e.append(ExprAssign(PC, ExprCond(cf, loc_next_expr, a))) - e.append(ExprAssign(ir.IRDst, ExprCond(cf, loc_next_expr, a))) + e.append(ExprAssign(PC, ExprCond(ExprOp("CC_U>=", cf ^ ExprInt(1, 1)), loc_next_expr, a))) + e.append(ExprAssign(ir.IRDst, ExprCond(ExprOp("CC_U>=", cf ^ ExprInt(1, 1)), loc_next_expr, a))) return e, [] @@ -323,8 +375,8 @@ def jge(ir, instr, a): loc_next = ir.get_next_loc_key(instr) loc_next_expr = ExprLoc(loc_next, 16) e = [] - e.append(ExprAssign(PC, ExprCond(nf ^ of, loc_next_expr, a))) - e.append(ExprAssign(ir.IRDst, ExprCond(nf ^ of, loc_next_expr, a))) + e.append(ExprAssign(PC, ExprCond(ExprOp("CC_S>=", nf, of), a, loc_next_expr))) + e.append(ExprAssign(ir.IRDst, ExprCond(ExprOp("CC_S>=", nf, of), a, loc_next_expr))) return e, [] @@ -340,7 +392,6 @@ def rrc_w(ir, instr, a): c = ExprCompose(a[1:16], cf) e.append(ExprAssign(a, c)) e.append(ExprAssign(cf, a[:1])) - # e += update_flag_zn_r(c) # micrcorruption e += update_flag_zf(a) @@ -357,7 +408,6 @@ def rra_w(ir, instr, a): e.append(ExprAssign(a, c)) # TODO: error in disasm microcorruption? # e.append(ExprAssign(cf, a[:1])) - # e += update_flag_zn_r(c) # micrcorruption e += update_flag_zf(a) @@ -373,7 +423,9 @@ def sxt(ir, instr, a): c = a[:8].signExtend(16) e.append(ExprAssign(a, c)) - e += update_flag_zn_r(c) + e += update_flag_zf(a) + e += update_flag_nf(a) + e += reset_sr_res() e += update_flag_cf_inv_zf(c) e.append(ExprAssign(of, ExprInt(0, 1))) diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py index 77744ccd..11c1e00f 100644 --- a/miasm2/arch/x86/arch.py +++ b/miasm2/arch/x86/arch.py @@ -540,7 +540,10 @@ class instruction_x86(instruction): self.additional_info.prefixed = getattr(c, "prefixed", "") def __str__(self): - o = super(instruction_x86, self).__str__() + return self.to_string() + + def to_string(self, loc_db=None): + o = super(instruction_x86, self).to_string(loc_db) if self.additional_info.g1.value & 1: o = "LOCK %s" % o if self.additional_info.g1.value & 2: diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index d775cff5..f0a9875e 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -20,16 +20,20 @@ class x86_32_CGen(CGen): self.translator = TranslatorC(self.ir_arch.loc_db) self.init_arch_C() - def gen_post_code(self, attrib): + def gen_post_code(self, attrib, pc_value): out = [] if attrib.log_regs: + # Update PC for dump_gpregs + out.append("%s = %s;" % (self.C_PC, pc_value)) out.append('dump_gpregs_32(jitcpu->cpu);') return out class x86_64_CGen(x86_32_CGen): - def gen_post_code(self, attrib): + def gen_post_code(self, attrib, pc_value): out = [] if attrib.log_regs: + # Update PC for dump_gpregs + out.append("%s = %s;" % (self.C_PC, pc_value)) out.append('dump_gpregs_64(jitcpu->cpu);') return out diff --git a/miasm2/core/asmbloc.py b/miasm2/core/asmbloc.py deleted file mode 100644 index 54760f4e..00000000 --- a/miasm2/core/asmbloc.py +++ /dev/null @@ -1,10 +0,0 @@ -""" -This module will be removed in favour of asmblock.py -Cause: French tipo. -""" -import warnings -from miasm2.core.asmblock import * - -warnings.warn('DEPRECATION WARNING: use "asmblock" sub-module instead of "asmbloc"') - -log_asmbloc = log_asmblock diff --git a/miasm2/core/bin_stream_ida.py b/miasm2/core/bin_stream_ida.py index de7bc971..f63077bf 100644 --- a/miasm2/core/bin_stream_ida.py +++ b/miasm2/core/bin_stream_ida.py @@ -1,5 +1,6 @@ from idc import Byte, SegEnd from idautils import Segments +from idaapi import is_mapped from miasm2.core.bin_stream import bin_stream_str @@ -14,7 +15,10 @@ class bin_stream_ida(bin_stream_str): def _getbytes(self, start, l=1): o = "" for ad in xrange(l): - o += chr(Byte(ad + start - self.shift)) + offset = ad + start - self.shift + if not is_mapped(offset): + raise IOError("not enough bytes") + o += chr(Byte(offset)) return o def readbs(self, l=1): diff --git a/miasm2/jitter/arch/JitCore_aarch64.c b/miasm2/jitter/arch/JitCore_aarch64.c index fc51848a..d8b6d0f9 100644 --- a/miasm2/jitter/arch/JitCore_aarch64.c +++ b/miasm2/jitter/arch/JitCore_aarch64.c @@ -194,6 +194,12 @@ PyObject * cpu_dump_gpregs(JitCpu* self, PyObject* args) } +PyObject * cpu_dump_gpregs_with_attrib(JitCpu* self, PyObject* args) +{ + return cpu_dump_gpregs(self, args); +} + + PyObject* cpu_set_exception(JitCpu* self, PyObject* args) { PyObject *item1; @@ -294,6 +300,8 @@ static PyMethodDef JitCpu_methods[] = { "X"}, {"dump_gpregs", (PyCFunction)cpu_dump_gpregs, METH_NOARGS, "X"}, + {"dump_gpregs_with_attrib", (PyCFunction)cpu_dump_gpregs_with_attrib, METH_VARARGS, + "X"}, {"get_gpreg", (PyCFunction)cpu_get_gpreg, METH_NOARGS, "X"}, {"set_gpreg", (PyCFunction)cpu_set_gpreg, METH_VARARGS, diff --git a/miasm2/jitter/arch/JitCore_arm.c b/miasm2/jitter/arch/JitCore_arm.c index 4f1fd254..dca341d3 100644 --- a/miasm2/jitter/arch/JitCore_arm.c +++ b/miasm2/jitter/arch/JitCore_arm.c @@ -157,6 +157,13 @@ PyObject * cpu_dump_gpregs(JitCpu* self, PyObject* args) } +PyObject * cpu_dump_gpregs_with_attrib(JitCpu* self, PyObject* args) +{ + return cpu_dump_gpregs(self, args); +} + + + PyObject* cpu_set_exception(JitCpu* self, PyObject* args) { PyObject *item1; @@ -276,6 +283,8 @@ static PyMethodDef JitCpu_methods[] = { "X"}, {"dump_gpregs", (PyCFunction)cpu_dump_gpregs, METH_NOARGS, "X"}, + {"dump_gpregs_with_attrib", (PyCFunction)cpu_dump_gpregs_with_attrib, METH_VARARGS, + "X"}, {"get_gpreg", (PyCFunction)cpu_get_gpreg, METH_NOARGS, "X"}, {"set_gpreg", (PyCFunction)cpu_set_gpreg, METH_VARARGS, diff --git a/miasm2/jitter/arch/JitCore_mep.c b/miasm2/jitter/arch/JitCore_mep.c index 44f36290..a089e84f 100644 --- a/miasm2/jitter/arch/JitCore_mep.c +++ b/miasm2/jitter/arch/JitCore_mep.c @@ -223,6 +223,10 @@ PyObject * cpu_dump_gpregs(JitCpu* self, PyObject* args) return Py_None; } +PyObject * cpu_dump_gpregs_with_attrib(JitCpu* self, PyObject* args) +{ + return cpu_dump_gpregs(self, args); +} PyObject* cpu_set_exception(JitCpu* self, PyObject* args) { @@ -244,10 +248,6 @@ PyObject* cpu_get_exception(JitCpu* self, PyObject* args) return PyLong_FromUnsignedLongLong((uint64_t)(((vm_cpu_t*)self->cpu)->exception_flags)); } - - - - void check_automod(JitCpu* jitcpu, uint64_t addr, uint64_t size) { PyObject *result; @@ -322,6 +322,7 @@ static PyMemberDef JitCpu_members[] = { static PyMethodDef JitCpu_methods[] = { {"init_regs", (PyCFunction)cpu_init_regs, METH_NOARGS, "X"}, {"dump_gpregs", (PyCFunction)cpu_dump_gpregs, METH_NOARGS, "X"}, + {"dump_gpregs_with_attrib", (PyCFunction)cpu_dump_gpregs_with_attrib, METH_VARARGS, "X"}, {"get_gpreg", (PyCFunction)cpu_get_gpreg, METH_NOARGS, "X"}, {"set_gpreg", (PyCFunction)cpu_set_gpreg, METH_VARARGS, "X"}, {"get_exception", (PyCFunction)cpu_get_exception, METH_VARARGS, "X"}, diff --git a/miasm2/jitter/arch/JitCore_msp430.c b/miasm2/jitter/arch/JitCore_msp430.c index 12a42782..69f179a4 100644 --- a/miasm2/jitter/arch/JitCore_msp430.c +++ b/miasm2/jitter/arch/JitCore_msp430.c @@ -158,6 +158,11 @@ PyObject * cpu_dump_gpregs(JitCpu* self, PyObject* args) return Py_None; } +PyObject * cpu_dump_gpregs_with_attrib(JitCpu* self, PyObject* args) +{ + return cpu_dump_gpregs(self, args); +} + PyObject* cpu_set_exception(JitCpu* self, PyObject* args) { @@ -259,6 +264,8 @@ static PyMethodDef JitCpu_methods[] = { "X"}, {"dump_gpregs", (PyCFunction)cpu_dump_gpregs, METH_NOARGS, "X"}, + {"dump_gpregs_with_attrib", (PyCFunction)cpu_dump_gpregs_with_attrib, METH_VARARGS, + "X"}, {"get_gpreg", (PyCFunction)cpu_get_gpreg, METH_NOARGS, "X"}, {"set_gpreg", (PyCFunction)cpu_set_gpreg, METH_VARARGS, diff --git a/miasm2/jitter/arch/JitCore_ppc32.c b/miasm2/jitter/arch/JitCore_ppc32.c index dfc46c91..e1a3fcd5 100644 --- a/miasm2/jitter/arch/JitCore_ppc32.c +++ b/miasm2/jitter/arch/JitCore_ppc32.c @@ -109,6 +109,12 @@ cpu_dump_gpregs(JitCpu *self, PyObject *args) { } PyObject * +cpu_dump_gpregs_with_attrib(JitCpu* self, PyObject* args) +{ + return cpu_dump_gpregs(self, args); +} + +PyObject * cpu_set_exception(JitCpu *self, PyObject *args) { PyObject *item1; uint64_t i; @@ -208,6 +214,7 @@ static PyMemberDef JitCpu_members[] = { static PyMethodDef JitCpu_methods[] = { {"init_regs", (PyCFunction)cpu_init_regs, METH_NOARGS, "X"}, {"dump_gpregs", (PyCFunction)cpu_dump_gpregs, METH_NOARGS, "X"}, + {"dump_gpregs_with_attrib", (PyCFunction)cpu_dump_gpregs_with_attrib, METH_VARARGS, "X"}, {"get_gpreg", (PyCFunction)cpu_get_gpreg, METH_NOARGS, "X"}, {"set_gpreg", (PyCFunction)cpu_set_gpreg, METH_VARARGS, "X"}, {"get_exception", (PyCFunction)cpu_get_exception, METH_VARARGS, "X"}, diff --git a/miasm2/jitter/arch/JitCore_x86.c b/miasm2/jitter/arch/JitCore_x86.c index b711f40b..fa47b324 100644 --- a/miasm2/jitter/arch/JitCore_x86.c +++ b/miasm2/jitter/arch/JitCore_x86.c @@ -349,6 +349,32 @@ PyObject * cpu_dump_gpregs(JitCpu* self, PyObject* args) } +PyObject * cpu_dump_gpregs_with_attrib(JitCpu* self, PyObject* args) +{ + vm_cpu_t* vmcpu; + PyObject *item1; + uint64_t attrib; + + if (!PyArg_ParseTuple(args, "O", &item1)) + RAISE(PyExc_TypeError,"Cannot parse arguments"); + + PyGetInt(item1, attrib); + + vmcpu = self->cpu; + if (attrib == 16 || attrib == 32) + dump_gpregs_32(vmcpu); + else if (attrib == 64) + dump_gpregs_64(vmcpu); + else { + RAISE(PyExc_TypeError,"Bad attrib"); + } + + Py_INCREF(Py_None); + return Py_None; +} + + + PyObject* cpu_set_exception(JitCpu* self, PyObject* args) { PyObject *item1; @@ -484,6 +510,8 @@ static PyMethodDef JitCpu_methods[] = { "X"}, {"dump_gpregs", (PyCFunction)cpu_dump_gpregs, METH_NOARGS, "X"}, + {"dump_gpregs_with_attrib", (PyCFunction)cpu_dump_gpregs_with_attrib, METH_VARARGS, + "X"}, {"get_gpreg", (PyCFunction)cpu_get_gpreg, METH_NOARGS, "X"}, {"set_gpreg", (PyCFunction)cpu_set_gpreg, METH_VARARGS, diff --git a/miasm2/jitter/codegen.py b/miasm2/jitter/codegen.py index 32af29a2..a9405472 100644 --- a/miasm2/jitter/codegen.py +++ b/miasm2/jitter/codegen.py @@ -392,11 +392,13 @@ class CGen(object): ) return out - def gen_post_code(self, attrib): + def gen_post_code(self, attrib, pc_value): """Callback to generate code AFTER the instruction execution @attrib: Attributes instance""" out = [] if attrib.log_regs: + # Update PC for dump_gpregs + out.append("%s = %s;" % (self.C_PC, pc_value)) out.append('dump_gpregs(jitcpu->cpu);') return out @@ -408,7 +410,7 @@ class CGen(object): out = [] if isinstance(dst, Expr): - out += self.gen_post_code(attrib) + out += self.gen_post_code(attrib, "DST_value") out.append('BlockDst->address = DST_value;') out += self.gen_post_instr_checks(attrib) out.append('\t\treturn JIT_RET_NO_EXCEPTION;') @@ -423,11 +425,11 @@ class CGen(object): offset in instr_offsets): # Only generate goto for next instructions. # (consecutive instructions) - out += self.gen_post_code(attrib) + out += self.gen_post_code(attrib, "0x%x" % offset) out += self.gen_post_instr_checks(attrib) out.append('goto %s;' % dst) else: - out += self.gen_post_code(attrib) + out += self.gen_post_code(attrib, "0x%x" % offset) out.append('BlockDst->address = DST_value;') out += self.gen_post_instr_checks(attrib) out.append('\t\treturn JIT_RET_NO_EXCEPTION;') diff --git a/miasm2/jitter/jitcore_python.py b/miasm2/jitter/jitcore_python.py index dd4c543e..0b1f5809 100644 --- a/miasm2/jitter/jitcore_python.py +++ b/miasm2/jitter/jitcore_python.py @@ -90,7 +90,7 @@ class JitCore_Python(jitcore.JitCore): # Log registers values if self.log_regs: exec_engine.update_cpu_from_engine() - exec_engine.cpu.dump_gpregs() + exec_engine.cpu.dump_gpregs_with_attrib(self.ir_arch.attrib) # Log instruction if self.log_mn: diff --git a/miasm2/jitter/llvmconvert.py b/miasm2/jitter/llvmconvert.py index 6f024c1e..37ce8d52 100644 --- a/miasm2/jitter/llvmconvert.py +++ b/miasm2/jitter/llvmconvert.py @@ -1292,8 +1292,14 @@ class LLVMFunction(object): self.printf("%.8X %s\n" % (instr_attrib.instr.offset, instr_attrib.instr.to_string(loc_db))) - def gen_post_code(self, attributes): + def gen_post_code(self, attributes, pc_value): if attributes.log_regs: + # Update PC for dump_gpregs + PC = self.llvm_context.PC + t_size = LLVMType.IntType(PC.size) + dst = self.builder.zext(t_size(pc_value), LLVMType.IntType(PC.size)) + self.affect(dst, PC) + fc_ptr = self.mod.get_global(self.llvm_context.logging_func) self.builder.call(fc_ptr, [self.local_vars["vmcpu"]]) @@ -1353,8 +1359,10 @@ class LLVMFunction(object): # We are no longer in the main stream, deactivate cache self.main_stream = False + offset = None if isinstance(dst, ExprInt): - loc_key = self.llvm_context.ir_arch.loc_db.get_or_create_offset_location(int(dst)) + offset = int(dst) + loc_key = self.llvm_context.ir_arch.loc_db.get_or_create_offset_location(offset) dst = ExprLoc(loc_key, dst.size) if isinstance(dst, ExprLoc): @@ -1371,7 +1379,7 @@ class LLVMFunction(object): if (offset in instr_offsets and offset > attrib.instr.offset): # forward local jump (ie. next instruction) - self.gen_post_code(attrib) + self.gen_post_code(attrib, offset) self.gen_post_instr_checks(attrib, offset) self.builder.branch(bbl) return @@ -1389,7 +1397,7 @@ class LLVMFunction(object): if dst.type.width != PC.size: dst = self.builder.zext(dst, LLVMType.IntType(PC.size)) - self.gen_post_code(attrib) + self.gen_post_code(attrib, offset) self.affect(dst, PC) self.gen_post_instr_checks(attrib, dst) self.affect(self.add_ir(ExprInt(0, 8)), ExprId("status", 32)) diff --git a/miasm2/jitter/vm_mngr_py.c b/miasm2/jitter/vm_mngr_py.c index 5ff436bf..93de9bb4 100644 --- a/miasm2/jitter/vm_mngr_py.c +++ b/miasm2/jitter/vm_mngr_py.c @@ -248,7 +248,6 @@ PyObject* vm_get_u8(VmMngr* self, PyObject* args) PyObject *py_addr; uint64_t addr; - uint64_t size; PyObject *obj_out; char * buf_out; int ret; @@ -276,7 +275,6 @@ PyObject* vm_get_u16(VmMngr* self, PyObject* args) PyObject *py_addr; uint64_t addr; - uint64_t size; PyObject *obj_out; char * buf_out; int ret; @@ -304,7 +302,6 @@ PyObject* vm_get_u32(VmMngr* self, PyObject* args) PyObject *py_addr; uint64_t addr; - uint64_t size; PyObject *obj_out; char * buf_out; int ret; @@ -333,7 +330,6 @@ PyObject* vm_get_u64(VmMngr* self, PyObject* args) PyObject *py_addr; uint64_t addr; - uint64_t size; PyObject *obj_out; char * buf_out; int ret; diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index 2110ccf7..c7d2961d 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -449,6 +449,13 @@ reg_tests_armt = [ ("00000000 UXTB R5, R0", "C5B2"), + + ("00000000 UXTAB R7, R0, R1", + "50FA81F7"), + + ("00000000 UXTAH R4, R0, R1", + "10FA81F4"), + ("xxxxxxxx BKPT 0x13", "13be"), ("xxxxxxxx SVC 0x13", @@ -493,6 +500,8 @@ reg_tests_armt = [ ("xxxxxxxx MOV R1, R1 LSL 0x10", "4FEA0141"), + ("xxxxxxxx MOV R2, R11 LSR 0x1", + "4FEA5B02"), ("xxxxxxxx ADD R1, R4, 0x30", "04F13001"), @@ -676,6 +685,9 @@ reg_tests_armt = [ ("xxxxxxxx DSB SY", "bff34f8f"), + ("xxxxxxxx CMP R5, R0 LSR 0x8", + "B5EB102F"), + ] print "#" * 40, 'armthumb', '#' * 40 diff --git a/test/test_all.py b/test/test_all.py index 4b97ffba..f3bcc477 100755 --- a/test/test_all.py +++ b/test/test_all.py @@ -21,6 +21,7 @@ TAGS = {"regression": "REGRESSION", # Regression tests "long": "LONG", # Very time consumming tests "llvm": "LLVM", # LLVM dependency is required "gcc": "GCC", # GCC based tests + "python": "PYTHON", # Python jitted tests "z3": "Z3", # Z3 dependency is needed "qemu": "QEMU", # QEMU tests (several tests) "cparser": "CPARSER", # pycparser is needed @@ -109,7 +110,7 @@ for script in ["x86/sem.py", continue testset += ArchUnitTest(script, jitter, base_dir="arch", tags=tags) -testset += ArchUnitTest("x86/unit/access_xmm.py", "python", base_dir="arch") +testset += ArchUnitTest("x86/unit/access_xmm.py", "python", base_dir="arch", tags=[TAGS["python"]]) ### QEMU regression tests class QEMUTest(RegressionTest): @@ -750,7 +751,7 @@ class ExampleJitterNoPython(ExampleJitter): for jitter in ExampleJitter.jitter_engines: # Take 5 min on a Core i5 - tags = {"python": [TAGS["long"]], + tags = {"python": [TAGS["long"], TAGS["python"]], "llvm": [TAGS["llvm"]], "gcc": [TAGS["gcc"]], } |