diff options
| -rw-r--r-- | example/disasm/full.py | 7 | ||||
| -rw-r--r-- | miasm/arch/x86/sem.py | 9 |
2 files changed, 9 insertions, 7 deletions
diff --git a/example/disasm/full.py b/example/disasm/full.py index 9e739109..47eca56d 100644 --- a/example/disasm/full.py +++ b/example/disasm/full.py @@ -240,9 +240,6 @@ if args.gen_ir: ircfg = ir_arch.new_ircfg() ircfg_a = ir_arch.new_ircfg() - ir_arch.blocks = {} - ir_arch_a.blocks = {} - head = list(entry_points)[0] for ad, asmcfg in viewitems(all_funcs_blocks): @@ -252,13 +249,13 @@ if args.gen_ir: ir_arch_a.add_asmblock_to_ircfg(block, ircfg_a) log.info("Print blocks (without analyse)") - for label, block in viewitems(ir_arch.blocks): + for label, block in viewitems(ircfg.blocks): print(block) log.info("Gen Graph... %x" % ad) log.info("Print blocks (with analyse)") - for label, block in viewitems(ir_arch_a.blocks): + for label, block in viewitems(ircfg_a.blocks): print(block) if args.simplify > 0: diff --git a/miasm/arch/x86/sem.py b/miasm/arch/x86/sem.py index 6e593f51..4e1e12e1 100644 --- a/miasm/arch/x86/sem.py +++ b/miasm/arch/x86/sem.py @@ -403,11 +403,16 @@ def gen_cmov(ir, instr, cond, dst, src, mov_if): dstA, dstB = loc_do_expr, loc_skip_expr else: dstA, dstB = loc_skip_expr, loc_do_expr - e = [m2_expr.ExprAssign(dst, dst)] + e = [] + if instr.mode == 64: + # Force destination set in order to zero high bit orders + # In 64 bit: + # cmovz eax, ebx + # if zf == 0 => high part of RAX is set to zero + e = [m2_expr.ExprAssign(dst, dst)] e_do, extra_irs = mov(ir, instr, dst, src) e_do.append(m2_expr.ExprAssign(ir.IRDst, loc_skip_expr)) e.append(m2_expr.ExprAssign(ir.IRDst, m2_expr.ExprCond(cond, dstA, dstB))) - e += set_float_cs_eip(instr) return e, [IRBlock(ir.loc_db, loc_do, [AssignBlock(e_do, instr)])] |