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-rw-r--r--miasm2/arch/aarch64/ira.py15
-rw-r--r--miasm2/arch/aarch64/jit.py23
-rw-r--r--miasm2/arch/arm/ira.py16
-rw-r--r--miasm2/arch/arm/jit.py23
-rw-r--r--miasm2/arch/mips32/ira.py34
-rw-r--r--miasm2/arch/mips32/jit.py19
-rw-r--r--miasm2/arch/msp430/ira.py32
-rw-r--r--miasm2/arch/msp430/jit.py16
-rw-r--r--miasm2/arch/x86/ira.py28
-rw-r--r--miasm2/arch/x86/jit.py53
10 files changed, 117 insertions, 142 deletions
diff --git a/miasm2/arch/aarch64/ira.py b/miasm2/arch/aarch64/ira.py
index e0dc8632..ada2e028 100644
--- a/miasm2/arch/aarch64/ira.py
+++ b/miasm2/arch/aarch64/ira.py
@@ -1,10 +1,7 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
-from miasm2.ir.ir import AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.aarch64.sem import ir_aarch64l, ir_aarch64b
-from miasm2.arch.aarch64.regs import *
 
 
 class ir_a_aarch64l_base(ir_aarch64l, ira):
@@ -28,13 +25,13 @@ class ir_a_aarch64l(ir_a_aarch64l_base):
         self.ret_reg = self.arch.regs.X0
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.cf)
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
 
-    def get_out_regs(self, b):
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
     def sizeof_char(self):
diff --git a/miasm2/arch/aarch64/jit.py b/miasm2/arch/aarch64/jit.py
index ca8d7b39..cd41cca8 100644
--- a/miasm2/arch/aarch64/jit.py
+++ b/miasm2/arch/aarch64/jit.py
@@ -2,7 +2,7 @@ import logging
 
 from miasm2.jitter.jitload import jitter, named_arguments
 from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core.utils import pck64, upck64
 from miasm2.arch.aarch64.sem import ir_aarch64b, ir_aarch64l
 
 log = logging.getLogger('jit_aarch64')
@@ -19,18 +19,17 @@ class jitter_aarch64l(jitter):
         jitter.__init__(self, ir_aarch64l(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint64_t(self, v):
+    def push_uint64_t(self, value):
         self.cpu.SP -= 8
-        self.vm.set_mem(self.cpu.SP, pck64(v))
+        self.vm.set_mem(self.cpu.SP, pck64(value))
 
     def pop_uint64_t(self):
-        x = upck32(self.vm.get_mem(self.cpu.SP, 8))
+        value = upck64(self.vm.get_mem(self.cpu.SP, 8))
         self.cpu.SP += 8
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck64(self.vm.get_mem(self.cpu.SP + 8 * n, 8))
-        return x
+    def get_stack_arg(self, index):
+        return upck64(self.vm.get_mem(self.cpu.SP + 8 * index, 8))
 
     # calling conventions
 
@@ -50,11 +49,11 @@ class jitter_aarch64l(jitter):
             self.cpu.X0 = ret_value
         return True
 
-    def get_arg_n_stdcall(self, n):
-        if n < self.max_reg_arg:
-            arg = self.cpu.get_gpreg()['X%d' % n]
+    def get_arg_n_stdcall(self, index):
+        if index < self.max_reg_arg:
+            arg = self.cpu.get_gpreg()['X%d' % index]
         else:
-            arg = self.get_stack_arg(n - self.max_reg_arg)
+            arg = self.get_stack_arg(index - self.max_reg_arg)
         return arg
 
     def init_run(self, *args, **kwargs):
diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py
index 7f5e8f1b..760e6d90 100644
--- a/miasm2/arch/arm/ira.py
+++ b/miasm2/arch/arm/ira.py
@@ -1,11 +1,7 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
-from miasm2.ir.ir import IRBlock, AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb
-from miasm2.arch.arm.regs import *
-# from miasm2.core.graph import DiGraph
 
 
 class ir_a_arml_base(ir_arml, ira):
@@ -26,13 +22,13 @@ class ir_a_arml(ir_a_arml_base):
         self.ret_reg = self.arch.regs.R0
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.cf)
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
 
-    def get_out_regs(self, b):
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
     def sizeof_char(self):
diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py
index 70d16176..9b5ddcbe 100644
--- a/miasm2/arch/arm/jit.py
+++ b/miasm2/arch/arm/jit.py
@@ -2,7 +2,7 @@ import logging
 
 from miasm2.jitter.jitload import jitter, named_arguments
 from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core.utils import pck32, upck32
 from miasm2.arch.arm.sem import ir_armb, ir_arml
 
 log = logging.getLogger('jit_arm')
@@ -18,18 +18,17 @@ class jitter_arml(jitter):
         jitter.__init__(self, ir_arml(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint32_t(self, v):
+    def push_uint32_t(self, value):
         self.cpu.SP -= 4
-        self.vm.set_mem(self.cpu.SP, pck32(v))
+        self.vm.set_mem(self.cpu.SP, pck32(value))
 
     def pop_uint32_t(self):
-        x = upck32(self.vm.get_mem(self.cpu.SP, 4))
+        value = upck32(self.vm.get_mem(self.cpu.SP, 4))
         self.cpu.SP += 4
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck32(self.vm.get_mem(self.cpu.SP + 4 * n, 4))
-        return x
+    def get_stack_arg(self, index):
+        return upck32(self.vm.get_mem(self.cpu.SP + 4 * index, 4))
 
     # calling conventions
 
@@ -49,11 +48,11 @@ class jitter_arml(jitter):
             self.cpu.R0 = ret_value
         return True
 
-    def get_arg_n_stdcall(self, n):
-        if n < 4:
-            arg = self.cpu.get_gpreg()['R%d' % n]
+    def get_arg_n_stdcall(self, index):
+        if index < 4:
+            arg = self.cpu.get_gpreg()['R%d' % index]
         else:
-            arg = self.get_stack_arg(n-4)
+            arg = self.get_stack_arg(index-4)
         return arg
 
     def init_run(self, *args, **kwargs):
diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py
index 67c5f2dc..bb51c055 100644
--- a/miasm2/arch/mips32/ira.py
+++ b/miasm2/arch/mips32/ira.py
@@ -1,10 +1,9 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
+from miasm2.expression.expression import ExprAff, ExprInt32, ExprId
 from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
-from miasm2.arch.mips32.regs import *
 from miasm2.core.asmbloc import expr_is_int_or_label, expr_is_label
 
 class ir_a_mips32l(ir_mips32l, ira):
@@ -12,23 +11,18 @@ class ir_a_mips32l(ir_mips32l, ira):
         ir_mips32l.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.V0
 
-
-    # for test XXX TODO
-    def set_dead_regs(self, b):
-        pass
-
     def pre_add_instr(self, block, instr, irb_cur, ir_blocks_all, gen_pc_updt):
         # Avoid adding side effects, already done in post_add_bloc
         return irb_cur
 
-    def post_add_bloc(self, bloc, ir_blocs):
-        IntermediateRepresentation.post_add_bloc(self, bloc, ir_blocs)
-        for irb in ir_blocs:
+    def post_add_bloc(self, block, ir_blocks):
+        IntermediateRepresentation.post_add_bloc(self, block, ir_blocks)
+        for irb in ir_blocks:
             pc_val = None
             lr_val = None
             for assignblk in irb.irs:
-                pc_val = assignblk.get(PC, pc_val)
-                lr_val = assignblk.get(RA, lr_val)
+                pc_val = assignblk.get(self.arch.regs.PC, pc_val)
+                lr_val = assignblk.get(self.arch.regs.RA, lr_val)
 
             if pc_val is None or lr_val is None:
                 continue
@@ -37,22 +31,22 @@ class ir_a_mips32l(ir_mips32l, ira):
             if expr_is_label(lr_val):
                 lr_val = ExprInt32(lr_val.name.offset)
 
-            l = bloc.lines[-2]
-            if lr_val.arg != l.offset + 8:
+            line = block.lines[-2]
+            if lr_val.arg != line.offset + 8:
                 raise ValueError("Wrong arg")
 
             # CALL
-            lbl = bloc.get_next()
+            lbl = block.get_next()
             new_lbl = self.gen_label()
-            irs = self.call_effects(pc_val, l)
+            irs = self.call_effects(pc_val, line)
             irs.append(AssignBlock([ExprAff(self.IRDst,
                                             ExprId(lbl, size=self.pc.size))]))
-            nbloc = IRBlock(new_lbl, irs)
-            nbloc.lines = [l] * len(irs)
-            self.blocs[new_lbl] = nbloc
+            nblock = IRBlock(new_lbl, irs)
+            nblock.lines = [line] * len(irs)
+            self.blocs[new_lbl] = nblock
             irb.dst = ExprId(new_lbl, size=self.pc.size)
 
-    def get_out_regs(self, b):
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
     def sizeof_char(self):
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
index 332e8d13..439209eb 100644
--- a/miasm2/arch/mips32/jit.py
+++ b/miasm2/arch/mips32/jit.py
@@ -2,7 +2,7 @@ import logging
 
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core.utils import pck32, upck32
 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
 from miasm2.jitter.codegen import CGen
 import miasm2.expression.expression as m2_expr
@@ -43,7 +43,7 @@ class mipsCGen(CGen):
             if not instr.breakflow():
                 continue
             for irblock in irblocks:
-                for i, assignblock in enumerate(irblock.irs):
+                for assignblock in irblock.irs:
                     if self.ir_arch.pc not in assignblock:
                         continue
                     # Add internal branch destination
@@ -68,7 +68,7 @@ class mipsCGen(CGen):
                                                 m2_expr.ExprId('branch_dst_irdst'),
                                                 m2_expr.ExprId('branch_dst_irdst'),
                                                 self.id_to_c(m2_expr.ExprInt(lbl.offset, 32)))
-               ).split('\n')
+              ).split('\n')
         return out
 
 
@@ -81,18 +81,17 @@ class jitter_mips32l(jitter):
         jitter.__init__(self, ir_mips32l(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint32_t(self, v):
+    def push_uint32_t(self, value):
         self.cpu.SP -= 4
-        self.vm.set_mem(self.cpu.SP, pck32(v))
+        self.vm.set_mem(self.cpu.SP, pck32(value))
 
     def pop_uint32_t(self):
-        x = upck32(self.vm.get_mem(self.cpu.SP, 4))
+        value = upck32(self.vm.get_mem(self.cpu.SP, 4))
         self.cpu.SP += 4
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck32(self.vm.get_mem(self.cpu.SP + 4 * n, 4))
-        return x
+    def get_stack_arg(self, index):
+        return upck32(self.vm.get_mem(self.cpu.SP + 4 * index, 4))
 
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
diff --git a/miasm2/arch/msp430/ira.py b/miasm2/arch/msp430/ira.py
index 46b0b5c9..0dc63c61 100644
--- a/miasm2/arch/msp430/ira.py
+++ b/miasm2/arch/msp430/ira.py
@@ -1,11 +1,7 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
-from miasm2.ir.ir import IRBlock, AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.msp430.sem import ir_msp430
-from miasm2.arch.msp430.regs import *
-# from miasm2.core.graph import DiGraph
 
 
 class ir_a_msp430_base(ir_msp430, ira):
@@ -21,19 +17,19 @@ class ir_a_msp430(ir_a_msp430_base):
         ir_a_msp430_base.__init__(self, symbol_pool)
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.cf)
-
-        b.rw[-1][1].add(self.arch.regs.res)
-        b.rw[-1][1].add(self.arch.regs.scg1)
-        b.rw[-1][1].add(self.arch.regs.scg0)
-        b.rw[-1][1].add(self.arch.regs.osc)
-        b.rw[-1][1].add(self.arch.regs.cpuoff)
-        b.rw[-1][1].add(self.arch.regs.gie)
-
-    def get_out_regs(self, b):
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
+
+        irblock.rw[-1][1].add(self.arch.regs.res)
+        irblock.rw[-1][1].add(self.arch.regs.scg1)
+        irblock.rw[-1][1].add(self.arch.regs.scg0)
+        irblock.rw[-1][1].add(self.arch.regs.osc)
+        irblock.rw[-1][1].add(self.arch.regs.cpuoff)
+        irblock.rw[-1][1].add(self.arch.regs.gie)
+
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
diff --git a/miasm2/arch/msp430/jit.py b/miasm2/arch/msp430/jit.py
index 95d34f96..74efdb98 100644
--- a/miasm2/arch/msp430/jit.py
+++ b/miasm2/arch/msp430/jit.py
@@ -1,6 +1,6 @@
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core.utils import pck16, upck16
 from miasm2.arch.msp430.sem import ir_msp430
 
 import logging
@@ -18,23 +18,23 @@ class jitter_msp430(jitter):
         jitter.__init__(self, ir_msp430(sp), *args, **kwargs)
         self.vm.set_little_endian()
 
-    def push_uint16_t(self, v):
+    def push_uint16_t(self, value):
         regs = self.cpu.get_gpreg()
         regs['SP'] -= 2
         self.cpu.set_gpreg(regs)
-        self.vm.set_mem(regs['SP'], pck16(v))
+        self.vm.set_mem(regs['SP'], pck16(value))
 
     def pop_uint16_t(self):
         regs = self.cpu.get_gpreg()
-        x = upck16(self.vm.get_mem(regs['SP'], 2))
+        value = upck16(self.vm.get_mem(regs['SP'], 2))
         regs['SP'] += 2
         self.cpu.set_gpreg(regs)
-        return x
+        return value
 
-    def get_stack_arg(self, n):
+    def get_stack_arg(self, index):
         regs = self.cpu.get_gpreg()
-        x = upck16(self.vm.get_mem(regs['SP'] + 2 * n, 2))
-        return x
+        value = upck16(self.vm.get_mem(regs['SP'] + 2 * index, 2))
+        return value
 
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
diff --git a/miasm2/arch/x86/ira.py b/miasm2/arch/x86/ira.py
index 5b80f5d5..1ff4cbe8 100644
--- a/miasm2/arch/x86/ira.py
+++ b/miasm2/arch/x86/ira.py
@@ -1,8 +1,6 @@
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import ExprAff, ExprOp, ExprId
-from miasm2.core.graph import DiGraph
-from miasm2.core.asmbloc import expr_is_label
+from miasm2.expression.expression import ExprAff, ExprOp
 from miasm2.ir.ir import AssignBlock
 from miasm2.ir.analysis import ira
 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64
@@ -15,21 +13,21 @@ class ir_a_x86_16(ir_x86_16, ira):
         self.ret_reg = self.arch.regs.AX
 
     # for test XXX TODO
-    def set_dead_regs(self, b):
-        b.rw[-1][1].add(self.arch.regs.zf)
-        b.rw[-1][1].add(self.arch.regs.of)
-        b.rw[-1][1].add(self.arch.regs.pf)
-        b.rw[-1][1].add(self.arch.regs.cf)
-        b.rw[-1][1].add(self.arch.regs.nf)
-        b.rw[-1][1].add(self.arch.regs.af)
-
-    def get_out_regs(self, b):
+    def set_dead_regs(self, irblock):
+        irblock.rw[-1][1].add(self.arch.regs.zf)
+        irblock.rw[-1][1].add(self.arch.regs.of)
+        irblock.rw[-1][1].add(self.arch.regs.pf)
+        irblock.rw[-1][1].add(self.arch.regs.cf)
+        irblock.rw[-1][1].add(self.arch.regs.nf)
+        irblock.rw[-1][1].add(self.arch.regs.af)
+
+    def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])
 
     def add_unused_regs(self):
-        leaves = [self.blocs[n] for n in self.g.leafs()]
-        for b in leaves:
-            self.set_dead_regs(b)
+        leaves = [self.blocs[label] for label in self.g.leafs()]
+        for irblock in leaves:
+            self.set_dead_regs(irblock)
 
 class ir_a_x86_32(ir_x86_32, ir_a_x86_16):
 
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py
index 2e483f2a..d8a244b2 100644
--- a/miasm2/arch/x86/jit.py
+++ b/miasm2/arch/x86/jit.py
@@ -2,7 +2,7 @@ import logging
 
 from miasm2.jitter.jitload import jitter, named_arguments
 from miasm2.core import asmbloc
-from miasm2.core.utils import *
+from miasm2.core.utils import pck16, pck32, pck64, upck16, upck32, upck64
 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64
 from miasm2.jitter.codegen import CGen
 
@@ -44,21 +44,20 @@ class jitter_x86_16(jitter):
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
         self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
 
-    def ir_archbloc_fix_regs_for_mode(self, irbloc, attrib=64):
-        self.orig_irbloc_fix_regs_for_mode(irbloc, 64)
+    def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64):
+        self.orig_irbloc_fix_regs_for_mode(irblock, 64)
 
-    def push_uint16_t(self, v):
+    def push_uint16_t(self, value):
         self.cpu.SP -= self.ir_arch.sp.size / 8
-        self.vm.set_mem(self.cpu.SP, pck16(v))
+        self.vm.set_mem(self.cpu.SP, pck16(value))
 
     def pop_uint16_t(self):
-        x = upck16(self.vm.get_mem(self.cpu.SP, self.ir_arch.sp.size / 8))
+        value = upck16(self.vm.get_mem(self.cpu.SP, self.ir_arch.sp.size / 8))
         self.cpu.SP += self.ir_arch.sp.size / 8
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck16(self.vm.get_mem(self.cpu.SP + 4 * n, 4))
-        return x
+    def get_stack_arg(self, index):
+        return upck16(self.vm.get_mem(self.cpu.SP + 4 * index, 4))
 
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
@@ -78,21 +77,20 @@ class jitter_x86_32(jitter):
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
         self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
 
-    def ir_archbloc_fix_regs_for_mode(self, irbloc, attrib=64):
-        self.orig_irbloc_fix_regs_for_mode(irbloc, 64)
+    def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64):
+        self.orig_irbloc_fix_regs_for_mode(irblock, 64)
 
-    def push_uint32_t(self, v):
+    def push_uint32_t(self, value):
         self.cpu.ESP -= self.ir_arch.sp.size / 8
-        self.vm.set_mem(self.cpu.ESP, pck32(v))
+        self.vm.set_mem(self.cpu.ESP, pck32(value))
 
     def pop_uint32_t(self):
-        x = upck32(self.vm.get_mem(self.cpu.ESP, self.ir_arch.sp.size / 8))
+        value = upck32(self.vm.get_mem(self.cpu.ESP, self.ir_arch.sp.size / 8))
         self.cpu.ESP += self.ir_arch.sp.size / 8
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck32(self.vm.get_mem(self.cpu.ESP + 4 * n, 4))
-        return x
+    def get_stack_arg(self, index):
+        return upck32(self.vm.get_mem(self.cpu.ESP + 4 * index, 4))
 
     # calling conventions
 
@@ -139,21 +137,20 @@ class jitter_x86_64(jitter):
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
         self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
 
-    def ir_archbloc_fix_regs_for_mode(self, irbloc, attrib=64):
-        self.orig_irbloc_fix_regs_for_mode(irbloc, 64)
+    def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64):
+        self.orig_irbloc_fix_regs_for_mode(irblock, 64)
 
-    def push_uint64_t(self, v):
+    def push_uint64_t(self, value):
         self.cpu.RSP -= self.ir_arch.sp.size / 8
-        self.vm.set_mem(self.cpu.RSP, pck64(v))
+        self.vm.set_mem(self.cpu.RSP, pck64(value))
 
     def pop_uint64_t(self):
-        x = upck64(self.vm.get_mem(self.cpu.RSP, self.ir_arch.sp.size / 8))
+        value = upck64(self.vm.get_mem(self.cpu.RSP, self.ir_arch.sp.size / 8))
         self.cpu.RSP += self.ir_arch.sp.size / 8
-        return x
+        return value
 
-    def get_stack_arg(self, n):
-        x = upck64(self.vm.get_mem(self.cpu.RSP + 8 * n, 8))
-        return x
+    def get_stack_arg(self, index):
+        return upck64(self.vm.get_mem(self.cpu.RSP + 8 * index, 8))
 
     @named_arguments
     def func_args_stdcall(self, n_args):