diff options
| -rw-r--r-- | miasm2/arch/aarch64/arch.py | 13 | ||||
| -rw-r--r-- | miasm2/arch/aarch64/sem.py | 123 | ||||
| -rw-r--r-- | miasm2/arch/x86/arch.py | 1126 | ||||
| -rw-r--r-- | test/arch/aarch64/arch.py | 1786 | ||||
| -rw-r--r-- | test/arch/x86/arch.py | 599 | ||||
| -rw-r--r-- | test/test_all.py | 1 |
6 files changed, 2956 insertions, 692 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py index b991fe81..a57b35bf 100644 --- a/miasm2/arch/aarch64/arch.py +++ b/miasm2/arch/aarch64/arch.py @@ -421,7 +421,7 @@ class instruction_aarch64(instruction): off = e.arg - self.offset if int(off % 4): raise ValueError('strange offset! %r' % off) - self.args[index] = m2_expr.ExprInt32(off) + self.args[index] = m2_expr.ExprInt64(off) @@ -929,17 +929,14 @@ class aarch64_gpreg_ext2(reg_noarg, m_arg): return self.parent.size.value def encode(self): - print "DECODE", self.expr if not isinstance(self.expr, m2_expr.ExprOp): return False arg0, arg1 = self.expr.args if not (isinstance(self.expr, m2_expr.ExprOp) and self.expr.op == 'segm'): return False - print 'OKI' if not arg0 in self.parent.rn.reg_info.expr: return False self.parent.rn.value = self.parent.rn.reg_info.expr.index(arg0) - print 'tt', arg0 is_reg = False self.parent.shift.value = 0 if isinstance(arg1, m2_expr.ExprId): @@ -950,14 +947,12 @@ class aarch64_gpreg_ext2(reg_noarg, m_arg): reg = arg1.args[0] else: return False - print 'ISR', is_reg if not (reg.size in gpregs_info and reg in gpregs_info[reg.size].expr): return False self.value = gpregs_info[reg.size].expr.index(reg) if is_reg: return True - print 'test int', arg1.args if not (isinstance(arg1.args[1], m2_expr.ExprInt)): return False if arg1.op not in EXT2_OP_INV: @@ -969,7 +964,6 @@ class aarch64_gpreg_ext2(reg_noarg, m_arg): if arg1.args[1].arg != self.get_size(): return False - print "RR", arg1.args[1].arg self.parent.shift.value = 1 @@ -1432,7 +1426,6 @@ class aarch64_b40(m_arg): size = self.parent.args[0].expr.size value = int(self.expr.arg) self.value = value & self.lmask - print 'TT', hex(value) if self.parent.sf.value is None: self.parent.sf.value = value >> self.l return True @@ -1626,7 +1619,7 @@ aarch64op("mvn", [sf, bs('01'), bs('01010'), shift, bs('1'), rm_sft, imm6, bs(' aarch64op("eor", [sf, bs('10'), bs('01010'), shift, bs('0'), rm_sft, imm6, rn, rd], [rd, rn, rm_sft]) aarch64op("eon", [sf, bs('10'), bs('01010'), shift, bs('1'), rm_sft, imm6, rn, rd], [rd, rn, rm_sft]) aarch64op("ands", [sf, bs('11'), bs('01010'), shift, bs('0'), rm_sft, imm6, rn, rd], [rd, rn, rm_sft]) -aarch64op("tst", [sf, bs('11'), bs('01010'), shift, bs('0'), rm_sft, imm6, rn, bs('11111')], [rn, rm_sft]) +aarch64op("tst", [sf, bs('11'), bs('01010'), shift, bs('0'), rm_sft, imm6, rn, bs('11111')], [rn, rm_sft], alias=True) aarch64op("bics", [sf, bs('11'), bs('01010'), shift, bs('1'), rm_sft, imm6, rn, rd], [rd, rn, rm_sft]) # move reg @@ -1776,7 +1769,7 @@ aarch64op("movk", [sf, bs('11'), bs('100101'), hw, imm16_hw_sc, rd], [rd, imm16_ ldstp_name = {'STP': 0b0, 'LDP': 0b1} bs_ldstp_name = bs_name(l=1, name=ldstp_name) aarch64op("ldstp", [sf, bs('0'), bs('101'), bs('0'), bs('0'), post_pre, bs('1'), bs_ldstp_name, simm7, rt2, rn64_deref_sf, rt], [rt, rt2, rn64_deref_sf]) -#aarch64op("ldstp", [sf, bs('0'), bs('101'), bs('0'), bs('0'), bs('1'), bs('0'), bs_ldstp_name, simm7, rt2, rn64_deref_sf, rt], [rt, rt2, rn64_deref_sf]) +aarch64op("ldstp", [sf, bs('0'), bs('101'), bs('0'), bs('0'), bs('1'), bs('0'), bs_ldstp_name, simm7, rt2, rn64_deref_sf, rt], [rt, rt2, rn64_deref_sf]) aarch64op("ldstp", [sdsize, bs('101'), bs('1'), bs('0'), post_pre, bs('1'), bs_ldstp_name, uimm7, sd2, rn64_deref_sd, sd1], [sd1, sd2, rn64_deref_sd]) aarch64op("ldstp", [sdsize, bs('101'), bs('1'), bs('0'), bs('1'), bs('0'), bs_ldstp_name, uimm7, sd2, rn64_deref_sd, sd1], [sd1, sd2, rn64_deref_sd]) diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index 800cc677..f23574e6 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -240,6 +240,13 @@ def ands(ir, instr, arg1, arg2, arg3): e.append(m2_expr.ExprAff(arg1, res)) return e, [] +def tst(ir, instr, arg1, arg2): + e = [] + arg2 = extend_arg(arg1, arg2) + res = arg1 & arg2 + e += update_flag_logic(res) + return e, [] + @sbuild.parse def lsl(arg1, arg2, arg3): @@ -383,10 +390,11 @@ def get_mem_access(mem): return addr, updt -def strb(ir, instr, arg1, arg2): + +def ldr(ir, instr, arg1, arg2): e = [] addr, updt = get_mem_access(arg2) - e.append(m2_expr.ExprAff(m2_expr.ExprMem(addr, 8), arg1[:8])) + e.append(m2_expr.ExprAff(arg1, m2_expr.ExprMem(addr, arg1.size))) if updt: e.append(updt) return e, [] @@ -402,7 +410,17 @@ def ldrb(ir, instr, arg1, arg2): return e, [] -def str(ir, instr, arg1, arg2): +def ldrh(ir, instr, arg1, arg2): + e = [] + addr, updt = get_mem_access(arg2) + e.append( + m2_expr.ExprAff(arg1, m2_expr.ExprMem(addr, 16).zeroExtend(arg1.size))) + if updt: + e.append(updt) + return e, [] + + +def l_str(ir, instr, arg1, arg2): e = [] addr, updt = get_mem_access(arg2) e.append(m2_expr.ExprAff(m2_expr.ExprMem(addr, arg1.size), arg1)) @@ -411,10 +429,19 @@ def str(ir, instr, arg1, arg2): return e, [] -def ldr(ir, instr, arg1, arg2): +def strb(ir, instr, arg1, arg2): e = [] addr, updt = get_mem_access(arg2) - e.append(m2_expr.ExprAff(arg1, m2_expr.ExprMem(addr, arg1.size))) + e.append(m2_expr.ExprAff(m2_expr.ExprMem(addr, 8), arg1[:8])) + if updt: + e.append(updt) + return e, [] + + +def strh(ir, instr, arg1, arg2): + e = [] + addr, updt = get_mem_access(arg2) + e.append(m2_expr.ExprAff(m2_expr.ExprMem(addr, 16), arg1[:16])) if updt: e.append(updt) return e, [] @@ -475,6 +502,19 @@ def ubfm(ir, instr, arg1, arg2, arg3, arg4): e.append(m2_expr.ExprAff(arg1, res)) return e, [] +def bfm(ir, instr, arg1, arg2, arg3, arg4): + e = [] + rim, sim = int(arg3.arg), int(arg4.arg) + 1 + if sim > rim: + res = arg2[rim:sim] + e.append(m2_expr.ExprAff(arg1[:sim-rim], res)) + else: + shift_i = arg2.size - rim + shift = m2_expr.ExprInt_from(arg2, shift_i) + res = arg2[:sim] + e.append(m2_expr.ExprAff(arg1[shift_i:shift_i+sim], res)) + return e, [] + @sbuild.parse def madd(arg1, arg2, arg3, arg4): @@ -482,6 +522,11 @@ def madd(arg1, arg2, arg3, arg4): @sbuild.parse +def msub(arg1, arg2, arg3, arg4): + arg1 = arg4 - (arg2 * arg3) + + +@sbuild.parse def udiv(arg1, arg2, arg3): arg1 = m2_expr.ExprOp('udiv', arg2, arg3) @@ -623,11 +668,20 @@ def br(arg1): def nop(): """Do nothing""" + + +@sbuild.parse +def extr(arg1, arg2, arg3, arg4): + compose = m2_expr.ExprCompose([(arg2, 0, arg2.size), + (arg3, arg2.size, arg2.size+arg3.size)]) + arg1 = compose[int(arg4.arg):int(arg4.arg)+arg1.size] + mnemo_func = sbuild.functions mnemo_func.update({ 'and': and_l, 'adds': adds, 'ands': ands, + 'tst': tst, 'subs': subs, 'cmp': cmp, 'cmn': cmn, @@ -653,19 +707,31 @@ mnemo_func.update({ 'stp': stp, 'ldp': ldp, - 'str': str, 'ldr': ldr, + 'ldrb': ldrb, + 'ldrh': ldrh, - 'ldur': ldr, # XXXX CHECK + 'ldur': ldr, + 'ldurb': ldrb, + 'ldurh': ldrh, + + 'str': l_str, + 'strb': strb, + 'strh': strh, + + 'stur': l_str, + 'sturb': strb, + 'sturh': strh, 'ldrsw': ldrsw, - 'strb': strb, - 'ldrb': ldrb, + 'bfm': bfm, 'sbfm': sbfm, 'ubfm': ubfm, + 'extr': extr, + }) @@ -698,12 +764,9 @@ class ir_aarch64l(ir): args[-1].args[0], args[-1].args[-1][:8].zeroExtend(32)) instr_ir, extra_ir = get_mnemo_expr(self, instr, *args) - # for i, expr in enumerate(instr_ir): - # instr_ir[i] = self.expraff_fix_regs_for_mode(expr) - # for b in extra_ir: - # for irs in b.irs: - # for i, expr in enumerate(irs): - # irs[i] = self.expraff_fix_regs_for_mode(expr) + self.mod_pc(instr, instr_ir, extra_ir) + instr_ir, extra_ir = self.del_dst_zr(instr, instr_ir, extra_ir) + return instr_ir, extra_ir def expr_fix_regs_for_mode(self, e): @@ -730,6 +793,36 @@ class ir_aarch64l(ir): irs[i] = self.expr_fix_regs_for_mode(e) irbloc.dst = self.expr_fix_regs_for_mode(irbloc.dst) + def mod_pc(self, instr, instr_ir, extra_ir): + "Replace PC by the instruction's offset" + cur_offset = m2_expr.ExprInt64(instr.offset) + for i, expr in enumerate(instr_ir): + dst, src = expr.dst, expr.src + if dst != self.pc: + dst = dst.replace_expr({self.pc: cur_offset}) + src = src.replace_expr({self.pc: cur_offset}) + instr_ir[i] = m2_expr.ExprAff(dst, src) + for b in extra_ir: + for irs in b.irs: + for i, expr in enumerate(irs): + dst, src = expr.dst, expr.src + if dst != self.pc: + dst = dst.replace_expr({self.pc: cur_offset}) + src = src.replace_expr({self.pc: cur_offset}) + irs[i] = m2_expr.ExprAff(dst, src) + + + def del_dst_zr(self, instr, instr_ir, extra_ir): + "Writes to zero register are discarded" + regs_to_fix = [WZR, XZR] + instr_ir = [expr for expr in instr_ir if expr.dst not in regs_to_fix] + + for b in extra_ir: + for i, irs in eunmerate(b.irs): + b.irs[i] = [expr for expr in irs if expr.dst not in regs_to_fix] + + return instr_ir, extra_ir + class ir_aarch64b(ir_aarch64l): diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py index f966c860..027d9a01 100644 --- a/miasm2/arch/x86/arch.py +++ b/miasm2/arch/x86/arch.py @@ -279,21 +279,25 @@ WORD = Literal('WORD') DWORD = Literal('DWORD') QWORD = Literal('QWORD') TBYTE = Literal('TBYTE') +XMMWORD = Literal('XMMWORD') +MEMPREFIX2SIZE = {'BYTE': 8, 'WORD': 16, 'DWORD': 32, + 'QWORD': 64, 'TBYTE': 80, 'XMMWORD': 128} + +SIZE2MEMPREFIX = dict((x[1], x[0]) for x in MEMPREFIX2SIZE.items()) def parse_deref_mem(s, l, t): - sz = {'BYTE': 8, 'WORD': 16, 'DWORD': 32, 'QWORD': 64, 'TBYTE': 80} t = t[0] if len(t) == 2: s, ptr = t - return ExprMem(ptr, sz[s[0]]) + return ExprMem(ptr, MEMPREFIX2SIZE[s[0]]) elif len(t) == 3: s, segm, ptr = t - return ExprMem(ExprOp('segm', segm[0], ptr), sz[s[0]]) + return ExprMem(ExprOp('segm', segm[0], ptr), MEMPREFIX2SIZE[s[0]]) else: raise ValueError('len(t) > 3') -mem_size = Group(BYTE | DWORD | QWORD | WORD | TBYTE) +mem_size = Group(BYTE | DWORD | QWORD | WORD | TBYTE | XMMWORD) deref_mem = Group(mem_size + PTR + Optional(Group(int_or_expr + COLON)) + deref_mem_ad).setParseAction(parse_deref_mem) @@ -478,22 +482,19 @@ class instruction_x86(instruction): return True if self.name.startswith('LOOP'): return True - # repxx yyy generate split flow - # if self.g1.value & 6 and self.name in repeat_mn: - # return True return self.name in ['CALL'] def dstflow2label(self, symbol_pool): if self.additional_info.g1.value & 6 and self.name in repeat_mn: return - e = self.args[0] - if isinstance(e, ExprId): - if not isinstance(e.name, asm_label) and e not in all_regs_ids: + expr = self.args[0] + if isinstance(expr, ExprId): + if not isinstance(expr.name, asm_label) and expr not in all_regs_ids: raise ValueError("ExprId must be a label or a register") - elif isinstance(e, ExprInt): - ad = e.arg + int(self.offset) + elif isinstance(expr, ExprInt): + ad = expr.arg + int(self.offset) l = symbol_pool.getby_offset_create(ad) - s = ExprId(l, e.size) + s = ExprId(l, expr.size) self.args[0] = s else: return @@ -509,9 +510,6 @@ class instruction_x86(instruction): return True if self.name.startswith('SYS'): return True - # repxx yyy generate split flow - # if self.g1.value & 6 and self.name in repeat_mn: - # return True return self.name in ['CALL', 'HLT', 'IRET', 'ICEBP'] def splitflow(self): @@ -525,9 +523,6 @@ class instruction_x86(instruction): return True if self.name.startswith('SYS'): return True - # repxx yyy generate split flow - # if self.g1.value & 6 and self.name in repeat_mn: - # return True return self.name in ['CALL'] def setdstflow(self, a): @@ -540,7 +535,6 @@ class instruction_x86(instruction): if self.additional_info.g1.value & 6 and self.name in repeat_mn: ad = int(self.offset) l = symbol_pool.getby_offset_create(ad) - # XXX size ??? s = ExprId(l, self.v_opmode()) return [s] return [self.args[0]] @@ -549,16 +543,14 @@ class instruction_x86(instruction): return self.mode def fixDstOffset(self): - e = self.args[0] + expr = self.args[0] if self.offset is None: raise ValueError('symbol not resolved %s' % l) - if not isinstance(e, ExprInt): - # raise ValueError('dst must be int or label') - log.warning('dynamic dst %r', e) + if not isinstance(expr, ExprInt): + log.warning('dynamic dst %r', expr) return - # return ExprInt32(e.arg - (self.offset + self.l)) self.args[0] = ExprInt_fromsize( - self.mode, e.arg - self.offset) + self.mode, expr.arg - self.offset) def get_info(self, c): self.additional_info.g1.value = c.g1.value @@ -589,28 +581,26 @@ class instruction_x86(instruction): return args @staticmethod - def arg2str(e, pos = None): - if isinstance(e, ExprId) or isinstance(e, ExprInt): - o = str(e) - elif isinstance(e, ExprMem): - sz = {8: 'BYTE', 16: 'WORD', 32: 'DWORD', - 64: 'QWORD', 80: 'TBYTE'}[e.size] + def arg2str(expr, pos=None): + if isinstance(expr, ExprId) or isinstance(expr, ExprInt): + o = str(expr) + elif isinstance(expr, ExprMem): + sz = SIZE2MEMPREFIX[expr.size] segm = "" - if e.is_op_segm(): - segm = "%s:" % e.arg.args[0] - e = e.arg.args[1] + if expr.is_op_segm(): + segm = "%s:" % expr.arg.args[0] + expr = expr.arg.args[1] else: - e = e.arg - if isinstance(e, ExprOp): - # s = str(e.arg)[1:-1] - s = str(e).replace('(', '').replace(')', '') + expr = expr.arg + if isinstance(expr, ExprOp): + s = str(expr).replace('(', '').replace(')', '') else: - s = str(e) + s = str(expr) o = sz + ' PTR %s[%s]' % (segm, s) - elif isinstance(e, ExprOp) and e.op == 'segm': - o = "%s:%s" % (e.args[0], e.args[1]) + elif isinstance(expr, ExprOp) and expr.op == 'segm': + o = "%s:%s" % (expr.args[0], expr.args[1]) else: - raise ValueError('check this %r' % e) + raise ValueError('check this %r' % expr) return "%s" % o @@ -723,7 +713,6 @@ class mn_x86(cls_mn): while True: c = v.getbytes(offset) if c == '\x66': - # pre_dis_info.opmode = 1 pre_dis_info['opmode'] = 1 elif c == '\x67': pre_dis_info['admode'] = 1 @@ -761,14 +750,12 @@ class mn_x86(cls_mn): break pre_dis_info['prefix'] += c offset += 1 - # pre_dis_info.b = v[:offset] return pre_dis_info, v, mode, offset, offset - offset_o @classmethod def get_cls_instance(cls, cc, mode, infos=None): for opmode in [0, 1]: for admode in [0, 1]: - # c = cls.all_mn_inst[cc][0] c = cc() c.init_class() @@ -803,18 +790,12 @@ class mn_x86(cls_mn): def reset_class(self): super(mn_x86, self).reset_class() - # self.rex_w.value, self.rex_b.value, - # self.rex_x.value = None, None, None - # self.opmode.value, self.admode.value = None, None if hasattr(self, "opmode"): del(self.opmode) if hasattr(self, "admode"): del(self.admode) - # self.opmode = 0 - # self.admode = 0 def add_pre_dis_info(self, pre_dis_info=None): - # print 'add_pre_dis_info', pre_dis_info if pre_dis_info is None: return True if hasattr(self, "prefixed") and self.prefixed.default == "\x66": @@ -917,10 +898,8 @@ class mn_x86(cls_mn): (c.g1.value & 2 or c.g1.value & 4 or c.opmode)): continue if hasattr(c, "fopmode") and v_opmode(c) != c.fopmode.mode: - # print 'DROP', c, v_opmode(c), c.fopmode.mode continue if hasattr(c, "fadmode") and v_admode(c) != c.fadmode.mode: - # print 'DROP', c, v_opmode(c), c.fopmode.mode continue # relative dstflow must not have opmode set # (affect IP instead of EIP for instance) @@ -932,7 +911,6 @@ class mn_x86(cls_mn): out.append((c, v)) candidates = out - # return [x[1][0] for x in candidates] for c, v in candidates: if v_opmode(c) == instr.mode: cand_same_mode += v @@ -960,7 +938,6 @@ class bs_modname_size(bs_divert): if mode in self.args['name']: nfields = fields[:] f, i = getfieldindexby_name(nfields, 'rex_w') - # f = bs("1", l=0, fname = 'rex_w') f = bs("1", l=0, cls=(bs_fbit,), fname="rex_w") osize = v_opmode_info(size, opmode, 1, 0) nfields[i] = f @@ -974,7 +951,6 @@ class bs_modname_size(bs_divert): nfields = fields[:] nfields = nfields[:-1] f, i = getfieldindexby_name(nfields, 'rex_w') - # f = bs("0", l=0, fname = 'rex_w') f = bs("0", l=0, cls=(bs_fbit,), fname="rex_w") osize = v_opmode_info(size, opmode, 0, 0) nfields[i] = f @@ -1110,9 +1086,8 @@ class x86_08_ne(x86_imm): v = swap_uint(self.l, v) p = self.parent admode = p.v_admode() - e = sign_ext(v, self.intsize, admode) - e = ExprInt_fromsize(admode, e) - self.expr = e + expr = sign_ext(v, self.intsize, admode) + self.expr = ExprInt_fromsize(admode, expr) return True @@ -1174,9 +1149,6 @@ class x86_s08to16(x86_imm): int(v & ((1 << self.in_size) - 1)), self.in_size, out_size): pass else: - # print 'cannot encode1', hex(v), - # print hex(sign_ext(int(v&((1<<self.in_size)-1)), - # self.in_size, out_size)) # test with rex_w self.parent.rex_w.value = 1 opmode = self.parent.v_opmode() @@ -1184,19 +1156,9 @@ class x86_s08to16(x86_imm): if (v != sign_ext( int(v & ((1 << self.in_size) - 1)), self.in_size, out_size)): - # print 'cannot encode2', hex(v), - # hex(sign_ext(int(v&((1<<self.in_size)-1)), - # self.in_size, out_size)) return False - else: - pass - else: - pass if v != sign_ext( int(v & ((1 << self.in_size) - 1)), self.in_size, out_size): - # print 'cannot encode3', hex(v), - # hex(sign_ext(int(v&((1<<self.in_size)-1)), self.in_size, - # self.out_size)) return False v = self.encodeval(v) self.value = (v & 0xffffffff) & self.lmask @@ -1225,29 +1187,16 @@ class x86_s08to32(x86_s08to16): v = ExprInt32(sign_ext(v, self.in_size, 32)) self.expr = v - # print "INT1", self.parent.rex_w.value, self.expr, self.expr.size return True -class x86_s08to64(x86_s08to16): +class x86_s08to64(x86_s08to32): in_size = 8 out_size = 64 def myexpr(self, x): return ExprInt64(x) - def decode(self, v): - v = v & self.lmask - v = self.decodeval(v) - if self.parent.rex_w.value == 1: - v = ExprInt64(sign_ext(v, self.in_size, 64)) - else: - v = ExprInt32(sign_ext(v, self.in_size, 32)) - - self.expr = v - # print "INT1X", self.parent.prefix.rex_w, self.expr, self.expr.size - return True - class x86_s32to64(x86_s08to32): in_size = 32 @@ -1264,40 +1213,38 @@ class bs_eax(m_arg): def decode(self, v): p = self.parent - e = None + expr = None if hasattr(p, 'w8') and p.w8.value == 0: - e = regs08_expr[self.rindex] + expr = regs08_expr[self.rindex] else: - e = size2gpregs[p.v_opmode()].expr[self.rindex] - self.expr = e + expr = size2gpregs[p.v_opmode()].expr[self.rindex] + self.expr = expr return True def encode(self): self.value = 0 p = self.parent - e = self.expr - # print "EEEEE", e, p.w8.value - # print 'XXX', p.mode, p.opmode + expr = self.expr osize = p.v_opmode() if hasattr(p, 'w8'): if p.w8.value is None: # XXX TODO: priority in w8 erase? - if e.size == 8: + if expr.size == 8: p.w8.value = 0 else: p.w8.value = 1 if hasattr(p, 'w8') and p.w8.value == 0: - return e == regs08_expr[self.rindex] + return expr == regs08_expr[self.rindex] elif p.mode in [16, 32]: - return e == size2gpregs[osize].expr[self.rindex] + return expr == size2gpregs[osize].expr[self.rindex] elif p.mode == 64: - if e == size2gpregs[64].expr[self.rindex]: + if expr == size2gpregs[64].expr[self.rindex]: p.rex_w.value = 1 return True - elif e == size2gpregs[osize].expr[self.rindex]: + elif expr == size2gpregs[osize].expr[self.rindex]: return True return False - + return False class bs_seg(m_arg): reg_info = r_eax_all @@ -1742,151 +1689,167 @@ def exprfindmod(e, o=None): raise ValueError('bad op') return None +def test_addr_size(ptr, size): + if isinstance(ptr, ExprInt): + return ptr.arg < (1 << size) + else: + return ptr.size == size + +SIZE2XMMREG = {64:gpregs_mm, + 128:gpregs_xmm} + +def parse_mem(expr, parent, w8, sx=0, xmm=0, mm=0): + dct_expr = {} + opmode = parent.v_opmode() + if expr.is_op_segm() and isinstance(expr.arg.args[0], ExprInt): + return None, None, False + + if expr.is_op_segm(): + segm = expr.arg.args[0] + ptr = expr.arg.args[1] + else: + segm = None + ptr = expr.arg -def expr2modrm(e, p, w8, sx=0, xmm=0, mm=0): - o = {} - if e.size == 64 and not e in gpregs_mm.expr: - if hasattr(p, 'sd'): - p.sd.value = 1 - # print 'set64pref', str(e) - elif hasattr(p, 'wd'): + dct_expr[f_isad] = True + ad_size = ptr.size + admode = parent.v_admode() + if not test_addr_size(ptr, admode): + return None, None, False + + if (w8 == 1 and expr.size != opmode and not sx and + not (hasattr(parent, 'sd') or hasattr(parent, 'wd'))): + return None, None, False + + if hasattr(parent, 'wd'): + if expr.size == 16: + parent.wd.value = 1 + elif expr.size == 32: pass - elif hasattr(p, 'stk'): + else: + return None, None, False + + if (parent.mode == 64 and ptr.size == 32 and + parent.admode != 1): + return None, None, False + dct_expr = {f_isad: True} + disp = exprfindmod(ptr, dct_expr) + out = [] + if disp is None: + # add 0 disp + disp = ExprInt32(0) + if disp is not None: + for signed, encoding, cast_int in [(True, f_s08, ExprInt8), + (True, f_s16, ExprInt16), + (True, f_s32, ExprInt32), + (False, f_u08, ExprInt8), + (False, f_u16, ExprInt16), + (False, f_u32, ExprInt32)]: + value = cast_int(int(disp.arg)) + if admode < value.size: + if signed: + if int(disp.arg) != sign_ext(int(value.arg), admode, disp.size): + continue + else: + if int(disp.arg) != int(value.arg): + continue + else: + if int(disp.arg) != sign_ext(int(value.arg), value.size, admode): + continue + x1 = dict(dct_expr) + x1[f_imm] = (encoding, value) + out.append(x1) + else: + out = [dct_expr] + return out, segm, True + +def expr2modrm(expr, parent, w8, sx=0, xmm=0, mm=0): + dct_expr = {f_isad : False} + + if mm or xmm: + if mm and expr.size != 64: + return None, None, False + elif xmm and expr.size != 128: + return None, None, False + + if isinstance(expr, ExprId): + selreg = SIZE2XMMREG[expr.size] + if not expr in selreg.expr: + return None, None, False + i = selreg.expr.index(expr) + dct_expr[i] = 1 + return [dct_expr], None, True + else: + return parse_mem(expr, parent, w8, sx, xmm, mm) + + elif expr.size == 64 and expr not in gpregs_mm.expr: + if hasattr(parent, 'sd'): + parent.sd.value = 1 + elif hasattr(parent, 'wd'): + pass + elif hasattr(parent, 'stk'): pass else: - p.rex_w.value = 1 - opmode = p.v_opmode() + parent.rex_w.value = 1 + opmode = parent.v_opmode() if sx == 1: opmode = 16 if sx == 2: opmode = 32 - if e.size == 8 and w8 != 0: + if expr.size == 8 and w8 != 0: return None, None, False - if w8 == 0 and e.size != 8: + if w8 == 0 and expr.size != 8: return None, None, False - if not isinstance(e, ExprMem): - o[f_isad] = False + if not isinstance(expr, ExprMem): + dct_expr[f_isad] = False if xmm: - if e in gpregs_xmm.expr: - i = gpregs_xmm.expr.index(e) - o[i] = 1 - return [o], None, True + if expr in gpregs_xmm.expr: + i = gpregs_xmm.expr.index(expr) + dct_expr[i] = 1 + return [dct_expr], None, True else: return None, None, False if mm: - if e in gpregs_mm.expr: - i = gpregs_mm.expr.index(e) - o[i] = 1 - return [o], None, True + if expr in gpregs_mm.expr: + i = gpregs_mm.expr.index(expr) + dct_expr[i] = 1 + return [dct_expr], None, True else: return None, None, False if w8 == 0: - # if (p.v_opmode() == 64 or p.rex_p.value == 1) and e in - # gpregs08_64.expr: - if p.mode == 64 and e in gpregs08_64.expr: + if parent.mode == 64 and expr in gpregs08_64.expr: r = gpregs08_64 - p.rex_p.value = 1 + parent.rex_p.value = 1 else: - p.rex_p.value = 0 - p.rex_x.value = 0 + parent.rex_p.value = 0 + parent.rex_x.value = 0 r = size2gpregs[8] - if not e in r.expr: + if not expr in r.expr: return None, None, False - i = r.expr.index(e) - o[i] = 1 - return [o], None, True - # print "ttt", opmode, e.size - if opmode != e.size: - # print "FFFF" + i = r.expr.index(expr) + dct_expr[i] = 1 + return [dct_expr], None, True + if opmode != expr.size: return None, None, False - if not e in size2gpregs[opmode].expr: + if not expr in size2gpregs[opmode].expr: return None, None, False - i = size2gpregs[opmode].expr.index(e) - # print 'aaa', p.mode, i + i = size2gpregs[opmode].expr.index(expr) if i > 7: - if p.mode == 64: - # p.rex_b.value = 1 - # i -=7 - # print "SET REXB" - pass - else: + if parent.mode != 64: return None, None, False - o[i] = 1 - return [o], None, True - if e.is_op_segm() and isinstance(e.arg.args[0], ExprInt): - return None, None, False - - if e.is_op_segm(): - segm = e.arg.args[0] - ptr = e.arg.args[1] - else: - segm = None - ptr = e.arg - - o[f_isad] = True - ad_size = ptr.size - admode = p.v_admode() - if ad_size != admode: - return None, None, False - """ - if e.size == 64: - if hasattr(p, 'sd'): - p.sd.value = 1 - else: - p.rex_w.value = 1 - """ - - if w8 == 1 and e.size != opmode: # p.v_opmode(): - if not (hasattr(p, 'sd') or hasattr(p, 'wd')): - return None, None, False - # print 'tttt' - - if hasattr(p, 'wd'): - s = e.size - if s == 16: - p.wd.value = 1 - elif s == 32: - pass - else: - return None, None, False - - if p.mode == 64 and ptr.size == 32: - if p.admode != 1: - return None, None, False - - o = {f_isad: True} - disp = exprfindmod(ptr, o) - out = [] - if disp is None: - # add 0 disp - disp = ExprInt32(0) - if disp is not None: - for s, x in [(f_s08, ExprInt8), (f_s16, ExprInt16), (f_s32, ExprInt32), - (f_u08, ExprInt8), (f_u16, ExprInt16), (f_u32, ExprInt32)]: - # print "1", disp - v = x(int(disp.arg)) - # print "2", v, hex(sign_ext(int(v.arg), v.size, disp.size)) - if int(disp.arg) != sign_ext(int(v.arg), v.size, disp.size): - # print 'nok' - continue - # print 'ok', s, v - x1 = dict(o) - x1[f_imm] = (s, v) - out.append(x1) - else: - out = [o] - return out, segm, True + dct_expr[i] = 1 + return [dct_expr], None, True + return parse_mem(expr, parent, w8, sx, xmm, mm) - -def modrm2expr(m, p, w8, sx=0, xmm=0, mm=0): +def modrm2expr(modrm, parent, w8, sx=0, xmm=0, mm=0): o = [] - if not m[f_isad]: - k = [x[0] for x in m.items() if x[1] == 1] - if len(k) != 1: - raise ValueError('strange reg encoding %r' % m) - k = k[0] + if not modrm[f_isad]: + modrm_k = [x[0] for x in modrm.iteritems() if x[1] == 1] + if len(modrm_k) != 1: + raise ValueError('strange reg encoding %r' % modrm) + modrm_k = modrm_k[0] if w8 == 0: opmode = 8 elif sx == 1: @@ -1894,48 +1857,42 @@ def modrm2expr(m, p, w8, sx=0, xmm=0, mm=0): elif sx == 2: opmode = 32 else: - opmode = p.v_opmode() - """ - if k > 7: - # XXX HACK TODO - e = size2gpregs[64].expr[k] - else: - e = size2gpregs[opmode].expr[k] - """ - # print 'yyy', opmode, k + opmode = parent.v_opmode() if xmm: - e = gpregs_xmm.expr[k] + expr = gpregs_xmm.expr[modrm_k] elif mm: - e = gpregs_mm.expr[k] - elif opmode == 8 and (p.v_opmode() == 64 or p.rex_p.value == 1): - e = gpregs08_64.expr[k] + expr = gpregs_mm.expr[modrm_k] + elif opmode == 8 and (parent.v_opmode() == 64 or parent.rex_p.value == 1): + expr = gpregs08_64.expr[modrm_k] else: - e = size2gpregs[opmode].expr[k] - return e - # print "enc", m, p.v_admode(), p.prefix.opmode, p.prefix.admode - admode = p.v_admode() - opmode = p.v_opmode() - for k, v in m.items(): - if type(k) in [int, long]: - e = size2gpregs[admode].expr[k] - if v != 1: - e = ExprInt_fromsize(admode, v) * e - o.append(e) - # print [str(x) for x in o] - if f_imm in m: - if p.disp.value is None: + expr = size2gpregs[opmode].expr[modrm_k] + return expr + admode = parent.v_admode() + opmode = parent.v_opmode() + for modrm_k, scale in modrm.items(): + if isinstance(modrm_k, (int, long)): + expr = size2gpregs[admode].expr[modrm_k] + if scale != 1: + expr = ExprInt_fromsize(admode, scale) * expr + o.append(expr) + if f_imm in modrm: + if parent.disp.value is None: return None - o.append(ExprInt_fromsize(admode, p.disp.expr.arg)) - e = ExprOp('+', *o) + o.append(ExprInt_fromsize(admode, parent.disp.expr.arg)) + expr = ExprOp('+', *o) if w8 == 0: opmode = 8 elif sx == 1: opmode = 16 elif sx == 2: opmode = 32 - e = ExprMem(e, size=opmode) - # print "mem size", opmode, e - return e + if xmm: + opmode = 128 + elif mm: + opmode = 64 + + expr = ExprMem(expr, size=opmode) + return expr class x86_rm_arg(m_arg): @@ -1943,11 +1900,10 @@ class x86_rm_arg(m_arg): def fromstring(self, s, parser_result=None): start, stop = super(x86_rm_arg, self).fromstring(s, parser_result) - e = self.expr p = self.parent if start is None: return None, None - s = e.size + s = self.expr.size return start, stop def get_modrm(self): @@ -1970,27 +1926,16 @@ class x86_rm_arg(m_arg): v = setmodrm(p.sib_scale.value, p.sib_index.value, p.sib_base.value) - # print 'SIB', hex(v) - # v |= p.rex_b.value << 8 - # v |= p.rex_x.value << 9 - # if v >= 0x100: - # pass xx = xx[v] return xx def decode(self, v): p = self.parent xx = self.get_modrm() - mm = hasattr(self.parent, "mm") - xmm = hasattr(self.parent, "xmm") - e = modrm2expr(xx, p, 1, xmm=xmm, mm=mm) - if e is None: - return False - self.expr = e - return True + self.expr = modrm2expr(xx, p, 1) + return self.expr is not None def gen_cand(self, v_cand, admode): - # print "GEN CAND" if not admode in modrm2byte: # XXX TODO: 64bit raise StopIteration @@ -2005,7 +1950,6 @@ class x86_rm_arg(m_arg): moddd = False for v in v_cand: new_v_cand.append(v) - # print 'CANDI', v, admode if f_imm in v and int(v[f_imm][1].arg) == 0: v = dict(v) del(v[f_imm]) @@ -2021,27 +1965,16 @@ class x86_rm_arg(m_arg): if f_imm in v: size, disp = v[f_imm] disp = int(disp.arg) - # disp = swap_uint(f_imm2size[size], int(disp)) v[f_imm] = size vo = v - # print 'vv', v, disp v = v.items() v.sort() v = tuple(v) - # print "II", e, admode - # print 'III', v - # if (8, 1) in v: - # pass if not v in modrm2byte[admode]: - # print 'cannot find' continue - # print "FOUND1", v xx = modrm2byte[admode][v] - # if opmode == 64 and admode == 64: - # pdb.set_trace() - # print "FOUND2", xx # default case for x in xx: if type(x) == tuple: @@ -2049,26 +1982,13 @@ class x86_rm_arg(m_arg): else: modrm = x sib = None - # print 'mod sib', hex(modrm), sib - # print p.sib_scale - # print p.sib_base - # print p.sib_index # 16 bit cannot have sib if (not sib is None) and admode == 16: continue - # if ((p.sib_scale and sib is None) or - # (p.sib_scale is None and sib)): - # log.debug('dif sib %r %r'%(p.sib_scale, sib)) - # continue - # print hex(modrm), sib - # p.mod.value, dum, p.rm.value = getmodrm(modrm) rex = modrm >> 8 # 0# XXX HACK REM temporary REX modrm>>8 if rex and admode != 64: continue - # print 'prefix', hex(rex) - # p.rex_x.value = o_rex_x - # p.rex_b.value = o_rex_b p.rex_x.value = (rex >> 1) & 1 p.rex_b.value = rex & 1 @@ -2082,44 +2002,12 @@ class x86_rm_arg(m_arg): # check re on parent if re != p.reg.value: continue - # p.mod.value.append(mod) - # p.rm.value.append(rm) if sib: - # print 'REX', p.rex_x.value, p.rex_b.value - # print hex(modrm), hex(sib) - # if (modrm & 0xFF == 4 and sib & 0xFF == 0x5 - # and p.rex_b.value ==1 and p.rex_x.value == 0): - # pass s_scale, s_index, s_base = getmodrm(sib) - # p.sib_scale.value, p.sib_index.value, - # p.sib_base.value = getmodrm(sib) - # p.sib_scale.decode(mod) - # p.sib_index.decode(re) - # p.sib_base.decode(rm) - # p.sib_scale.value.append(mod) - # p.sib_index.value.append(re) - # p.sib_base.value.append(rm) else: - # p.sib_scale.value.append(None) - # p.sib_index.value.append(None) - # p.sib_base.value.append(None) s_scale, s_index, s_base = None, None, None - # print 'IIII', repr(p.disp), f_imm in v - # if p.disp and not f_imm in vo: - # continue - # if not p.disp and f_imm in vo: - # continue - # if p.disp: - # if p.disp.l != f_imm2size[vo[f_imm]]: - # continue - # print "DISP", repr(p.disp), p.disp.l - # p.disp.value = int(disp.arg) - # print 'append' - # print mod, rm, s_scale, s_index, s_base, disp - # print p.mod, p.rm - # out_c.append((mod, rm, s_scale, s_index, s_base, disp)) p.mod.value = mod p.rm.value = rm p.sib_scale.value = s_scale @@ -2134,19 +2022,14 @@ class x86_rm_arg(m_arg): raise StopIteration def encode(self): - e = self.expr - # print "eee", e - if isinstance(e, ExprInt): + if isinstance(self.expr, ExprInt): raise StopIteration p = self.parent admode = p.v_admode() - mode = e.size - mm = hasattr(self.parent, 'mm') - xmm = hasattr(self.parent, 'xmm') - v_cand, segm, ok = expr2modrm(e, p, 1, xmm=xmm, mm=mm) + mode = self.expr.size + v_cand, segm, ok = expr2modrm(self.expr, p, 1) if segm: p.g2.value = segm2enc[segm] - # print "REZ1", v_cand, ok for x in self.gen_cand(v_cand, admode): yield x @@ -2156,28 +2039,23 @@ class x86_rm_w8(x86_rm_arg): def decode(self, v): p = self.parent xx = self.get_modrm() - e = modrm2expr(xx, p, p.w8.value) - self.expr = e - return e is not None + self.expr = modrm2expr(xx, p, p.w8.value) + return self.expr is not None def encode(self): - e = self.expr - if isinstance(e, ExprInt): + if isinstance(self.expr, ExprInt): raise StopIteration p = self.parent if p.w8.value is None: - if e.size == 8: + if self.expr.size == 8: p.w8.value = 0 else: p.w8.value = 1 - # print 'TTTTT', e - v_cand, segm, ok = expr2modrm(e, p, p.w8.value) + v_cand, segm, ok = expr2modrm(self.expr, p, p.w8.value) if segm: p.g2.value = segm2enc[segm] - # print "REZ2", v_cand, ok for x in self.gen_cand(v_cand, p.v_admode()): - # print 'REZ', p.rex_x.value yield x @@ -2186,21 +2064,19 @@ class x86_rm_sx(x86_rm_arg): def decode(self, v): p = self.parent xx = self.get_modrm() - e = modrm2expr(xx, p, p.w8.value, 1) - self.expr = e - return e is not None + self.expr = modrm2expr(xx, p, p.w8.value, 1) + return self.expr is not None def encode(self): - e = self.expr - if isinstance(e, ExprInt): + if isinstance(self.expr, ExprInt): raise StopIteration p = self.parent if p.w8.value is None: - if e.size == 8: + if self.expr.size == 8: p.w8.value = 0 else: p.w8.value = 1 - v_cand, segm, ok = expr2modrm(e, p, p.w8.value, 1) + v_cand, segm, ok = expr2modrm(self.expr, p, p.w8.value, 1) if segm: p.g2.value = segm2enc[segm] for x in self.gen_cand(v_cand, p.v_admode()): @@ -2212,16 +2088,14 @@ class x86_rm_sxd(x86_rm_arg): def decode(self, v): p = self.parent xx = self.get_modrm() - e = modrm2expr(xx, p, 1, 2) - self.expr = e - return e is not None + self.expr = modrm2expr(xx, p, 1, 2) + return self.expr is not None def encode(self): - e = self.expr - if isinstance(e, ExprInt): + if isinstance(self.expr, ExprInt): raise StopIteration p = self.parent - v_cand, segm, ok = expr2modrm(e, p, 1, 2) + v_cand, segm, ok = expr2modrm(self.expr, p, 1, 2) if segm: p.g2.value = segm2enc[segm] for x in self.gen_cand(v_cand, p.v_admode()): @@ -2229,85 +2103,89 @@ class x86_rm_sxd(x86_rm_arg): class x86_rm_sd(x86_rm_arg): + out_size = 64 + def get_s_value(self): + return self.parent.sd.value + def set_s_value(self, value): + self.parent.sd.value = value def decode(self, v): p = self.parent xx = self.get_modrm() - e = modrm2expr(xx, p, 1) - if not isinstance(e, ExprMem): + expr = modrm2expr(xx, p, 1) + if not isinstance(expr, ExprMem): return False - if p.sd.value == 0: - e = ExprMem(e.arg, 32) + if self.get_s_value() == 0: + expr = ExprMem(expr.arg, 32) else: - e = ExprMem(e.arg, 64) - self.expr = e - return e is not None + expr = ExprMem(expr.arg, self.out_size) + self.expr = expr + return self.expr is not None def encode(self): - e = self.expr - if isinstance(e, ExprInt): + if isinstance(self.expr, ExprInt): raise StopIteration p = self.parent - if not e.size in [32, 64]: + if not self.expr.size in [32, 64]: raise StopIteration - p.sd.value = 0 - v_cand, segm, ok = expr2modrm(e, p, 1) + self.set_s_value(0) + v_cand, segm, ok = expr2modrm(self.expr, p, 1) for x in self.gen_cand(v_cand, p.v_admode()): yield x -class x86_rm_wd(x86_rm_arg): - - def decode(self, v): - p = self.parent - xx = self.get_modrm() - e = modrm2expr(xx, p, 1) - if not isinstance(e, ExprMem): - return False - if p.wd.value == 0: - e = ExprMem(e.arg, 32) - else: - e = ExprMem(e.arg, 16) - self.expr = e - return e is not None +class x86_rm_wd(x86_rm_sd): + out_size = 16 + def get_s_value(self): + return self.parent.wd.value + def set_s_value(self, value): + self.parent.wd.value = value def encode(self): - e = self.expr - if isinstance(e, ExprInt): + if isinstance(self.expr, ExprInt): raise StopIteration p = self.parent p.wd.value = 0 - v_cand, segm, ok = expr2modrm(e, p, 1) + v_cand, segm, ok = expr2modrm(self.expr, p, 1) for x in self.gen_cand(v_cand, p.v_admode()): yield x -class x86_rm_m80(x86_rm_arg): - msize = 80 +class x86_rm_m64(x86_rm_arg): + msize = 64 def decode(self, v): p = self.parent xx = self.get_modrm() - # print "aaa", xx - e = modrm2expr(xx, p, 1) - if not isinstance(e, ExprMem): + expr = modrm2expr(xx, p, 1) + if not isinstance(expr, ExprMem): return False - e = ExprMem(e.arg, self.msize) - self.expr = e - return e is not None + self.expr = ExprMem(expr.arg, self.msize) + return self.expr is not None + + def encode(self): + if isinstance(self.expr, ExprInt): + raise StopIteration + p = self.parent + v_cand, segm, ok = expr2modrm(self.expr, p, 0, 0, 0, 1) + for x in self.gen_cand(v_cand, p.v_admode()): + yield x + + +class x86_rm_m80(x86_rm_m64): + msize = 80 def encode(self): - e = self.expr - if isinstance(e, ExprInt): + if isinstance(self.expr, ExprInt): raise StopIteration - if not isinstance(e, ExprMem) or e.size != self.msize: + if not isinstance(self.expr, ExprMem) or self.expr.size != self.msize: raise StopIteration p = self.parent mode = p.mode if mode == 64: mode = 32 - e = ExprMem(e.arg, mode) - v_cand, segm, ok = expr2modrm(e, p, 1) + self.expr = ExprMem(self.expr.arg, mode) + v_cand, segm, ok = expr2modrm(self.expr, p, 1) for x in self.gen_cand(v_cand, p.v_admode()): yield x @@ -2318,24 +2196,15 @@ class x86_rm_m08(x86_rm_arg): def decode(self, v): p = self.parent xx = self.get_modrm() - e = modrm2expr(xx, p, 0) - self.expr = e - return e is not None + self.expr = modrm2expr(xx, p, 0) + return self.expr is not None def encode(self): - e = self.expr - if e.size != 8: - raise StopIteration - """ - if not isinstance(e, ExprMem) or e.size != self.msize: + if self.expr.size != 8: raise StopIteration - """ p = self.parent mode = p.mode - # if mode == 64: - # mode = 32 - # e = ExprMem(e.arg, mode) - v_cand, segm, ok = expr2modrm(e, p, 0) + v_cand, segm, ok = expr2modrm(self.expr, p, 0) for x in self.gen_cand(v_cand, p.v_admode()): yield x @@ -2344,8 +2213,62 @@ class x86_rm_m16(x86_rm_m80): msize = 16 -class x86_rm_m64(x86_rm_m80): +class x86_rm_mm(x86_rm_m80): + msize = 64 + is_mm = True + is_xmm = False + + def decode(self, v): + p = self.parent + xx = self.get_modrm() + expr = modrm2expr(xx, p, 0, 0, self.is_xmm, self.is_mm) + if isinstance(expr, ExprMem) and expr.size != self.msize: + expr = ExprMem(expr.arg, self.msize) + self.expr = expr + return True + + + def encode(self): + expr = self.expr + if isinstance(expr, ExprInt): + raise StopIteration + if isinstance(expr, ExprMem) and expr.size != self.msize: + raise StopIteration + p = self.parent + mode = p.mode + if mode == 64: + mode = 32 + if isinstance(expr, ExprMem): + if self.is_xmm: + expr = ExprMem(expr.arg, 128) + elif self.is_mm: + expr = ExprMem(expr.arg, 64) + + v_cand, segm, ok = expr2modrm(expr, p, 0, 0, self.is_xmm, self.is_mm) + for x in self.gen_cand(v_cand, p.v_admode()): + yield x + + +class x86_rm_mm_m64(x86_rm_mm): msize = 64 + is_mm = True + is_xmm = False + +class x86_rm_xmm(x86_rm_mm): + msize = 128 + is_mm = False + is_xmm = True + + +class x86_rm_xmm_m32(x86_rm_mm): + msize = 32 + is_mm = False + is_xmm = True + +class x86_rm_xmm_m64(x86_rm_mm): + msize = 64 + is_mm = False + is_xmm = True class x86_rm_reg_noarg(object): @@ -2354,12 +2277,10 @@ class x86_rm_reg_noarg(object): parser = gpreg def fromstring(self, s, parser_result=None): - # print 'parsing reg', s, opmode if not hasattr(self.parent, 'sx') and hasattr(self.parent, "w8"): self.parent.w8.value = 1 if parser_result: e, start, stop = parser_result[self.parser] - # print 'reg result', e, start, stop if e is None: return None, None self.expr = e @@ -2378,7 +2299,6 @@ class x86_rm_reg_noarg(object): return None, None self.parent.w8.value = 0 - # print 'parsed', s, self.expr return start, stop def getrexsize(self): @@ -2391,31 +2311,15 @@ class x86_rm_reg_noarg(object): v = v & self.lmask p = self.parent opmode = p.v_opmode() - # if hasattr(p, 'sx'): - # opmode = 16 if not hasattr(p, 'sx') and (hasattr(p, 'w8') and p.w8.value == 0): opmode = 8 r = size2gpregs[opmode] if p.mode == 64 and self.getrexsize(): v |= 0x8 - # print "XXX", p.v_opmode(), p.rex_p.value if p.v_opmode() == 64 or p.rex_p.value == 1: if not hasattr(p, 'sx') and (hasattr(p, 'w8') and p.w8.value == 0): - # if (hasattr(p, 'w8') and p.w8.value == 0): r = gpregs08_64 - """ - if v < 8: - self.expr = r.expr[v] - else: - self.expr = size2gpregs[64].expr[v] - """ - if hasattr(p, "xmm") or hasattr(p, "xmmreg"): - e = gpregs_xmm.expr[v] - elif hasattr(p, "mm") or hasattr(p, "mmreg"): - e = gpregs_mm.expr[v] - else: - e = r.expr[v] - self.expr = e + self.expr = r.expr[v] return True def encode(self): @@ -2423,12 +2327,7 @@ class x86_rm_reg_noarg(object): return False if self.expr in gpregs64.expr and not hasattr(self.parent, 'stk'): self.parent.rex_w.value = 1 - # print self.parent.opmode - # fd opmode = self.parent.v_opmode() - # if hasattr(self.parent, 'sx'): - # opmode = 16 - # print 'reg encode', self.expr, opmode if not hasattr(self.parent, 'sx') and hasattr(self.parent, 'w8'): self.parent.w8.value = 1 if self.expr.size == 8: @@ -2437,14 +2336,7 @@ class x86_rm_reg_noarg(object): self.parent.w8.value = 0 opmode = 8 r = size2gpregs[opmode] - # print "YYY", opmode, self.expr - if ((hasattr(self.parent, 'xmm') or hasattr(self.parent, 'xmmreg')) - and self.expr in gpregs_xmm.expr): - i = gpregs_xmm.expr.index(self.expr) - elif ((hasattr(self.parent, 'mm') or hasattr(self.parent, 'mmreg')) - and self.expr in gpregs_mm.expr): - i = gpregs_mm.expr.index(self.expr) - elif self.expr in r.expr: + if self.expr in r.expr: i = r.expr.index(self.expr) elif (opmode == 8 and self.parent.mode == 64 and self.expr in gpregs08_64.expr): @@ -2453,28 +2345,48 @@ class x86_rm_reg_noarg(object): else: log.debug("cannot encode reg %r", self.expr) return False - # print "zzz", opmode, self.expr, i, self.parent.mode if self.parent.v_opmode() == 64: if i > 7: self.setrexsize(1) i -= 8 elif self.parent.mode == 64 and i > 7: i -= 8 - # print 'rrr', self.getrexsize() - # self.parent.rex_b.value = 1 self.setrexsize(1) - if hasattr(self.parent, 'xmm') or hasattr(self.parent, 'mm'): - if i > 7: - i -= 8 self.value = i if self.value > self.lmask: log.debug("cannot encode field value %x %x", self.value, self.lmask) return False - # print 'RR ok' return True +class x86_rm_reg_mm(x86_rm_reg_noarg, m_arg): + selreg = gpregs_mm + def decode(self, v): + if self.parent.mode == 64 and self.getrexsize(): + v |= 0x8 + self.expr = self.selreg.expr[v] + return True + + def encode(self): + if not isinstance(self.expr, ExprId): + return False + if self.expr not in self.selreg.expr: + return False + i = self.selreg.expr.index(self.expr) + if self.parent.mode == 64 and i > 7: + i -= 8 + self.setrexsize(1) + self.value = i + if self.value > self.lmask: + log.debug("cannot encode field value %x %x", + self.value, self.lmask) + return False + return True + +class x86_rm_reg_xmm(x86_rm_reg_mm): + selreg = gpregs_xmm + class x86_rm_reg(x86_rm_reg_noarg, m_arg): pass @@ -2525,7 +2437,6 @@ class bs_fbit(bsi): def decode(self, v): # value already decoded in pre_dis_info - # print "jj", self.value return True @@ -2594,9 +2505,6 @@ class bs_cond_disp(bs_cond): @classmethod def flen(cls, mode, v): - # print 'disp cond', mode, - # print v, v_admode_info(mode, v['opmode'], v['admode']) - # if v_admode_info(mode, v['opmode'], v['admode']) ==16: if admode_prefix((mode, v['opmode'], v['admode'])) == 16: if v['mod'] == 0b00: if v['rm'] == 0b110: @@ -2655,26 +2563,23 @@ class bs_cond_imm(bs_cond_scale, m_arg): def fromstring(self, s, parser_result=None): if parser_result: - e, start, stop = parser_result[self.parser] + expr, start, stop = parser_result[self.parser] else: try: - e, start, stop = self.parser.scanString(s).next() + expr, start, stop = self.parser.scanString(s).next() except StopIteration: - e = None - self.expr = e + expr = None + self.expr = expr if len(self.parent.args) > 1: l = self.parent.args[0].expr.size else: l = self.parent.v_opmode() - # l = min(l, self.max_size) - # l = offsize(self.parent) if isinstance(self.expr, ExprInt): v = int(self.expr.arg) mask = ((1 << l) - 1) v = v & mask - e = ExprInt_fromsize(l, v) - self.expr = e + self.expr = ExprInt_fromsize(l, v) if self.expr is None: log.debug('cannot fromstring int %r', s) @@ -2687,8 +2592,6 @@ class bs_cond_imm(bs_cond_scale, m_arg): if 'se' in v and v['se'] == 1: return 8 else: - # osize = v_opmode_info(mode, v['opmode'], v['admode']) - # osize = opmode_prefix((mode, v['opmode'], v['admode'])) osize = v_opmode_info(mode, v['opmode'], v['rex_w'], 0) osize = min(osize, cls.max_size) return osize @@ -2710,12 +2613,9 @@ class bs_cond_imm(bs_cond_scale, m_arg): self.l = l mask = ((1 << self.l) - 1) - # print 'ext', self.l, l, hex(v), hex(sign_ext(v & ((1<<self.l)-1), - # self.l, l)) if v != sign_ext(v & mask, self.l, l): raise StopIteration self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) - # print hex(self.value) yield True raise StopIteration @@ -2723,10 +2623,8 @@ class bs_cond_imm(bs_cond_scale, m_arg): if arg0_expr.size == 64: self.parent.rex_w.value = 1 - l = self.parent.v_opmode() # self.parent.args[0].expr.size - # print 'imm enc', l, self.parent.rex_w.value + l = self.parent.v_opmode() v = int(self.expr.arg) - # print "imms size", l, hex(v), arg0_expr.size if arg0_expr.size == 8: if not hasattr(self.parent, 'w8'): raise StopIteration @@ -2737,11 +2635,8 @@ class bs_cond_imm(bs_cond_scale, m_arg): elif hasattr(self.parent, 'se'): if hasattr(self.parent, 'w8'): self.parent.w8.value = 1 - # print 'test', 8, hex(v), - # print hex(sign_ext(v & 0xFF, 8, arg0_expr.size)) # try to generate signed extended version if v == sign_ext(v & 0xFF, 8, arg0_expr.size): - # print 'setse' self.parent.se.value = 1 self.l = 8 self.value = v & 0xFF @@ -2754,15 +2649,11 @@ class bs_cond_imm(bs_cond_scale, m_arg): self.l = self.getmaxlen() else: self.l = l - # l = min(l, self.max_size) mask = ((1 << self.l) - 1) - # print 'ext', self.l, l, hex(v), hex(sign_ext(v & ((1<<self.l)-1), - # self.l, l)) if v != sign_ext(v & mask, self.l, l): raise StopIteration self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) - # print hex(self.value) yield True def decode(self, v): @@ -2775,7 +2666,6 @@ class bs_cond_imm(bs_cond_scale, m_arg): v = sign_ext(v, self.l, l_out) v = ExprInt_fromsize(l_out, v) self.expr = v - # print self.expr, repr(self.expr) return True @@ -2797,25 +2687,24 @@ class bs_cond_imm64(bs_cond_imm): return 8 -class bs_rel_off(bs_cond_imm): # m_arg): +class bs_rel_off(bs_cond_imm): parser = int_or_expr def fromstring(self, s, parser_result=None): if parser_result: - e, start, stop = parser_result[self.parser] + expr, start, stop = parser_result[self.parser] else: try: - e, start, stop = self.parser.scanString(s).next() + expr, start, stop = self.parser.scanString(s).next() except StopIteration: - e = None - self.expr = e + expr = None + self.expr = expr l = self.parent.mode if isinstance(self.expr, ExprInt): v = int(self.expr.arg) mask = ((1 << l) - 1) v = v & mask - e = ExprInt_fromsize(l, v) - self.expr = e + self.expr = ExprInt_fromsize(l, v) return start, stop @classmethod @@ -2833,12 +2722,8 @@ class bs_rel_off(bs_cond_imm): # m_arg): if self.l != 0: l = self.l else: - l = self.parent.v_opmode() # self.parent.args[0].expr.size + l = self.parent.v_opmode() self.l = l - # if l == 16: - # self.l = 16 - # else: - # self.l = 32 l = offsize(self.parent) prefix = self.parent.gen_prefix() parent_len = len(prefix) * 8 + self.parent.l + self.l @@ -2924,20 +2809,16 @@ class bs_moff(bsi): raise StopIteration if not isinstance(m.args[1], ExprInt): raise StopIteration - l = self.parent.v_opmode() # self.parent.args[0].expr.size + l = self.parent.v_opmode() if l == 16: self.l = 16 else: self.l = 32 - # print 'imm enc', l, self.parent.rex_w.value v = int(m.args[1].arg) mask = ((1 << self.l) - 1) - # print 'ext', self.l, l, hex(v), hex(sign_ext(v & ((1<<self.l)-1), - # self.l, l)) if v != sign_ext(v & mask, self.l, l): raise StopIteration self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) - # print hex(self.value) yield True def decode(self, v): @@ -2949,7 +2830,6 @@ class bs_moff(bsi): v = sign_ext(v, self.l, opmode) v = ExprInt_fromsize(opmode, v) self.expr = v - # print self.expr, repr(self.expr) return True @@ -2961,7 +2841,6 @@ class bs_movoff(m_arg): e, start, stop = parser_result[self.parser] if e is None: return None, None - # print 'fromstring', hex(e), self.int2expr if not isinstance(e, ExprMem): return None, None self.expr = e @@ -2974,11 +2853,10 @@ class bs_movoff(m_arg): return None, None if not isinstance(e, ExprMem): return None, None - e = v[0] - if e is None: + self.expr = v[0] + if self.expr is None: log.debug('cannot fromstring int %r', s) return None, None - self.expr = e return start, stop @classmethod @@ -2992,13 +2870,11 @@ class bs_movoff(m_arg): return asize def encode(self): - e = self.expr p = self.parent - if not isinstance(e, ExprMem) or not isinstance(e.arg, ExprInt): + if not isinstance(self.expr, ExprMem) or not isinstance(self.expr.arg, ExprInt): raise StopIteration self.l = p.v_admode() - # print 'imm enc', l, self.parent.rex_w.value - v = int(e.arg.arg) + v = int(self.expr.arg.arg) mask = ((1 << self.l) - 1) if v != mask & v: raise StopIteration @@ -3021,7 +2897,6 @@ class bs_movoff(m_arg): if self.parent.w8.value == 0: size = 8 self.expr = ExprMem(v, size) - # print self.expr, repr(self.expr) return True @@ -3041,11 +2916,10 @@ class bs_msegoff(m_arg): v, start, stop = self.parser.scanString(s).next() except StopIteration: return None, None - e = v[0] - if e is None: + self.expr = v[0] + if self.expr is None: log.debug('cannot fromstring int %r', s) return None, None - self.expr = e return start, stop def encode(self): @@ -3055,12 +2929,9 @@ class bs_msegoff(m_arg): raise StopIteration if not isinstance(self.expr.args[1], ExprInt): raise StopIteration - l = self.parent.v_opmode() # self.parent.args[0].expr.size - # print 'imm enc', l, self.parent.rex_w.value + l = self.parent.v_opmode() v = int(self.expr.args[0].arg) mask = ((1 << self.l) - 1) - # print 'ext', self.l, l, hex(v), hex(sign_ext(v & ((1<<self.l)-1), - # self.l, l)) if v != sign_ext(v & mask, self.l, l): raise StopIteration self.value = swap_uint(self.l, v & ((1 << self.l) - 1)) @@ -3070,11 +2941,8 @@ class bs_msegoff(m_arg): opmode = self.parent.v_opmode() v = swap_uint(self.l, v) self.value = v - #v = sign_ext(v, self.l, opmode) v = ExprInt16(v) - e = ExprOp('segm', v, self.parent.off.expr) - self.expr = e - # print self.expr, repr(self.expr) + self.expr = ExprOp('segm', v, self.parent.off.expr) return True @@ -3152,11 +3020,9 @@ class field_size: d_imm64 = bs(l=0, fname="imm64") -# d_eax = bs_eax(l=0) d_eax = bs(l=0, cls=(bs_eax, ), fname='eax') d_edx = bs(l=0, cls=(bs_edx, ), fname='edx') d_st = bs(l=0, cls=(x86_reg_st, ), fname='st') -# d_imm = bs(l=0, cls=(bs_cond_imm,), fname="imm") d_imm = bs(l=0, cls=(bs_cond_imm,), fname="imm") d_imm64 = bs(l=0, cls=(bs_cond_imm64,), fname="imm") d_ax = bs(l=0, cls=(r_ax, ), fname='ax') @@ -3186,6 +3052,11 @@ segm = bs(l=3, cls=(x86_rm_segm, ), order =1, fname = "reg") crreg = bs(l=3, cls=(x86_rm_cr, ), order =1, fname = "reg") drreg = bs(l=3, cls=(x86_rm_dr, ), order =1, fname = "reg") + +mm_reg = bs(l=3, cls=(x86_rm_reg_mm, ), order =1, fname = "reg") +xmm_reg = bs(l=3, cls=(x86_rm_reg_xmm, ), order =1, fname = "reg") + + fltreg = bs(l=3, cls=(x86_rm_flt, ), order =1, fname = "reg") rm = bs(l=3, fname="rm") @@ -3196,11 +3067,18 @@ rm_arg_sx = bs(l=0, cls=(x86_rm_sx,), fname='rmarg') rm_arg_sxd = bs(l=0, cls=(x86_rm_sxd,), fname='rmarg') rm_arg_sd = bs(l=0, cls=(x86_rm_sd,), fname='rmarg') rm_arg_wd = bs(l=0, cls=(x86_rm_wd,), fname='rmarg') -rm_arg_m80 = bs(l=0, cls=(x86_rm_m80,), fname='rmarg') rm_arg_m64 = bs(l=0, cls=(x86_rm_m64,), fname='rmarg') +rm_arg_m80 = bs(l=0, cls=(x86_rm_m80,), fname='rmarg') rm_arg_m08 = bs(l=0, cls=(x86_rm_m08,), fname='rmarg') rm_arg_m16 = bs(l=0, cls=(x86_rm_m16,), fname='rmarg') +rm_arg_mm = bs(l=0, cls=(x86_rm_mm,), fname='rmarg') +rm_arg_mm_m64 = bs(l=0, cls=(x86_rm_mm_m64,), fname='rmarg') + +rm_arg_xmm = bs(l=0, cls=(x86_rm_xmm,), fname='rmarg') +rm_arg_xmm_m32 = bs(l=0, cls=(x86_rm_xmm_m32,), fname='rmarg') +rm_arg_xmm_m64 = bs(l=0, cls=(x86_rm_xmm_m64,), fname='rmarg') + swapargs = bs_swapargs(l=1, fname="swap", mn_mod=range(1 << 1)) @@ -3291,7 +3169,6 @@ class bs_ad_mode(bsi): def decode(self, v): admode = self.parent.v_admode() - # print "MODE", opmode, self.mode return admode == self.mode @@ -3306,7 +3183,6 @@ class bs_op_mode_no64(bsi): if self.parent.mode == 64: return False opmode = self.parent.v_opmode() - # print "MODE", opmode, self.mode return opmode == self.mode @@ -3349,10 +3225,6 @@ bs_opmode32_no64 = bs(l=0, cls=(bs_op_mode_no64,), mode = 32, fname="fopmode") bs_mode64 = bs(l=0, cls=(bs_op_mode64,)) bs_modeno64 = bs(l=0, cls=(bs_op_modeno64,)) -# class ia32_call(mn_x86): -# fields = [bs8(0xff)] + rmmod(d3) -# conv_name = {16:'CBW', 32:'CWDE', 64:'CDQE'} -# bs_conv_name = bs_modname_size(l=0, name=conv_name) addop("cbw", [bs8(0x98), bs_opmode16]) addop("cwde", [bs8(0x98), bs_opmode32]) addop("cdqe", [bs8(0x98), bs_opmode64]) @@ -3372,9 +3244,6 @@ addop("cmp", [bs("001110"), swapargs, w8] + addop("cmpsb", [bs8(0xa6)]) -# cmps_name = {16:'CMPSW', 32:'CMPSD', 64:'CMPSQ'} -# bs_cmps_name = bs_modname_size(l=0, name=cmps_name) -# addop("cmps", [bs8(0xa7), bs_cmps_name]) addop("cmpsw", [bs8(0xa7), bs_opmode16]) addop("cmpsd", [bs8(0xa7), bs_opmode32]) addop("cmpsq", [bs8(0xa7), bs_opmode64]) @@ -3384,9 +3253,6 @@ addop("cmpxchg", [bs8(0x0f), bs('1011000'), w8] # XXX TODO CMPXCHG8/16 addop("cpuid", [bs8(0x0f), bs8(0xa2)]) -# convbis_name = {16:'CWD', 32:'CDQ', 64:'CQO'} -# bs_convbis_name = bs_modname_size(l=0, name=convbis_name) -# addop("convbis", [bs8(0x99), bs_convbis_name]) addop("cwd", [bs8(0x99), bs_opmode16]) addop("cdq", [bs8(0x99), bs_opmode32]) addop("cqo", [bs8(0x99), bs_opmode64]) @@ -3575,9 +3441,6 @@ addop("inc", [bs('1111111'), w8] + rmmod(d0, rm_arg_w8)) addop("inc", [bs('01000'), reg]) addop("insb", [bs8(0x6c)]) -# ins_name = {16:'INSW', 32:'INSD', 64:'INSD'} -# bs_ins_name = bs_modname_size(l=0, name=ins_name) -# addop("ins", [bs8(0x6d), bs_ins_name]) addop("insw", [bs8(0x6d), bs_opmode16]) addop("insd", [bs8(0x6d), bs_opmode32]) addop("insd", [bs8(0x6d), bs_opmode64]) @@ -3588,16 +3451,11 @@ addop("into", [bs8(0xce)]) addop("invd", [bs8(0x0f), bs8(0x08)]) addop("invlpg", [bs8(0x0f), bs8(0x01)] + rmmod(d7)) -# iret_name = {16:'IRET', 32:'IRETD', 64:'IRETQ'} -# bs_iret_name = bs_modname_size(l=0, name=iret_name) -# addop("iret", [bs8(0xcf), stk, bs_iret_name]) addop("iret", [bs8(0xcf), bs_opmode16]) addop("iretd", [bs8(0xcf), bs_opmode32]) addop("iretq", [bs8(0xcf), bs_opmode64]) addop("j", [bs('0111'), cond, rel_off08]) -# bs_jecxz_name = bs_modname_jecx(l=0) -# addop("jecxz", [bs8(0xe3), rel_off08, bs_jecxz_name]) addop("jcxz", [bs8(0xe3), rel_off08, bs_admode16]) addop("jecxz", [bs8(0xe3), rel_off08, bs_admode32]) @@ -3625,9 +3483,6 @@ addop("lgs", [bs8(0x0f), bs8(0xb5)] + rmmod(rmreg)) addop("leave", [bs8(0xc9), stk]) addop("lodsb", [bs8(0xac)]) -# lods_name = {16:'LODSW', 32:'LODSD', 64:'LODSQ'} -# bs_lods_name = bs_modname_size(l=0, name=lods_name) -# addop("lods", [bs8(0xad), bs_lods_name]) addop("lodsw", [bs8(0xad), bs_opmode16]) addop("lodsd", [bs8(0xad), bs_opmode32]) addop("lodsq", [bs8(0xad), bs_opmode64]) @@ -3649,9 +3504,6 @@ addop("mov", [bs8(0x0f), bs("001000"), swapargs, bs('0')] addop("mov", [bs8(0x0f), bs("001000"), swapargs, bs('1')] + rmmod(drreg), [rm_arg, drreg]) addop("movsb", [bs8(0xa4)]) -# movs_name = {16:'MOVSW', 32:'MOVSD', 64:'MOVSQ'} -# bs_movs_name = bs_modname_size(l=0, name=movs_name) -# addop("movs", [bs8(0xa5), bs_movs_name]) addop("movsw", [bs8(0xa5), bs_opmode16]) addop("movsd", [bs8(0xa5), bs_opmode32]) addop("movsq", [bs8(0xa5), bs_opmode64]) @@ -3660,62 +3512,62 @@ addop("movsx", [bs8(0x0f), bs("1011111"), w8, sx] + rmmod(rmreg, rm_arg_sx)) addop("movsxd", [bs8(0x63), sxd, bs_mode64] + rmmod(rmreg, rm_arg_sxd)) addop("movups", - [bs8(0x0f), bs8(0x10), xmm, no_xmm_pref] + rmmod(rmreg, rm_arg)) -addop("movsd", [bs8(0x0f), bs("0001000"), swapargs, xmm, pref_f2] - + rmmod(rmreg, rm_arg), [xmm, rm_arg]) -addop("movss", [bs8(0x0f), bs("0001000"), swapargs, xmm, pref_f3] + - rmmod(rmreg, rm_arg), [rmreg, rm_arg]) -addop("movupd", [bs8(0x0f), bs8(0x10), xmm, pref_66] + rmmod(rmreg, rm_arg)) + [bs8(0x0f), bs8(0x10), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm)) +addop("movsd", [bs8(0x0f), bs("0001000"), swapargs, pref_f2] + + rmmod(xmm_reg, rm_arg_xmm_m64), [xmm_reg, rm_arg_xmm_m64]) +addop("movss", [bs8(0x0f), bs("0001000"), swapargs, pref_f3] + + rmmod(xmm_reg, rm_arg_xmm_m32), [xmm_reg, rm_arg_xmm_m32]) +addop("movupd", [bs8(0x0f), bs8(0x10), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) -addop("movd", [bs8(0x0f), bs('011'), swapargs, bs('1110'), mm, no_xmm_pref] + - rmmod(rmreg, rm_arg), [rmreg, rm_arg]) -addop("movd", [bs8(0x0f), bs('011'), swapargs, bs('1110'), xmm, pref_66] + - rmmod(rmreg, rm_arg), [rmreg, rm_arg]) +addop("movd", [bs8(0x0f), bs('011'), swapargs, bs('1110'), no_xmm_pref] + + rmmod(mm_reg, rm_arg), [mm_reg, rm_arg]) +addop("movd", [bs8(0x0f), bs('011'), swapargs, bs('1110'), pref_66] + + rmmod(xmm_reg, rm_arg), [xmm_reg, rm_arg]) -addop("movq", [bs8(0x0f), bs('011'), swapargs, bs('1111'), mm, no_xmm_pref] + - rmmod(rmreg, rm_arg), [rmreg, rm_arg]) +addop("movq", [bs8(0x0f), bs('011'), swapargs, bs('1111'), no_xmm_pref] + + rmmod(mm_reg, rm_arg_mm_m64), [mm_reg, rm_arg_mm_m64]) -addop("movq", [bs8(0x0f), bs8(0x7e), xmm, pref_f3] + - rmmod(rmreg, rm_arg), [rmreg, rm_arg]) -addop("movq", [bs8(0x0f), bs8(0xd6), xmm, pref_66] + - rmmod(rmreg, rm_arg), [rm_arg, rmreg]) +addop("movq", [bs8(0x0f), bs8(0x7e), pref_f3] + + rmmod(xmm_reg, rm_arg_xmm_m64), [xmm_reg, rm_arg_xmm_m64]) +addop("movq", [bs8(0x0f), bs8(0xd6), pref_66] + + rmmod(xmm_reg, rm_arg_xmm_m64), [rm_arg_xmm_m64, xmm_reg]) -addop("addss", [bs8(0x0f), bs8(0x58), xmm, pref_f3] + rmmod(rmreg, rm_arg)) -addop("addsd", [bs8(0x0f), bs8(0x58), xmm, pref_f2] + rmmod(rmreg, rm_arg)) +addop("addss", [bs8(0x0f), bs8(0x58), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32)) +addop("addsd", [bs8(0x0f), bs8(0x58), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64)) -addop("subss", [bs8(0x0f), bs8(0x5c), xmm, pref_f3] + rmmod(rmreg, rm_arg)) -addop("subsd", [bs8(0x0f), bs8(0x5c), xmm, pref_f2] + rmmod(rmreg, rm_arg)) +addop("subss", [bs8(0x0f), bs8(0x5c), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32)) +addop("subsd", [bs8(0x0f), bs8(0x5c), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64)) -addop("mulss", [bs8(0x0f), bs8(0x59), xmm, pref_f3] + rmmod(rmreg, rm_arg)) -addop("mulsd", [bs8(0x0f), bs8(0x59), xmm, pref_f2] + rmmod(rmreg, rm_arg)) +addop("mulss", [bs8(0x0f), bs8(0x59), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32)) +addop("mulsd", [bs8(0x0f), bs8(0x59), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64)) -addop("divss", [bs8(0x0f), bs8(0x5e), xmm, pref_f3] + rmmod(rmreg, rm_arg)) -addop("divsd", [bs8(0x0f), bs8(0x5e), xmm, pref_f2] + rmmod(rmreg, rm_arg)) +addop("divss", [bs8(0x0f), bs8(0x5e), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32)) +addop("divsd", [bs8(0x0f), bs8(0x5e), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64)) -addop("pminsw", [bs8(0x0f), bs8(0xea), mm, no_xmm_pref] + rmmod(rmreg, rm_arg)) -addop("pminsw", [bs8(0x0f), bs8(0xea), xmm, pref_66] + rmmod(rmreg, rm_arg)) +addop("pminsw", [bs8(0x0f), bs8(0xea), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm)) +addop("pminsw", [bs8(0x0f), bs8(0xea), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) -addop("pxor", [bs8(0x0f), bs8(0xef), xmm] + rmmod(rmreg, rm_arg)) +addop("pxor", [bs8(0x0f), bs8(0xef), xmm] + rmmod(xmm_reg, rm_arg_xmm)) -addop("ucomiss", - [bs8(0x0f), bs8(0x2e), xmm, no_xmm_pref] + rmmod(rmreg, rm_arg)) -addop("ucomisd", [bs8(0x0f), bs8(0x2e), xmm, pref_66] + rmmod(rmreg, rm_arg)) +addop("ucomiss", [bs8(0x0f), bs8(0x2e), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm_m32)) +addop("ucomisd", [bs8(0x0f), bs8(0x2e), pref_66] + rmmod(xmm_reg, rm_arg_xmm_m64)) -addop("andps", [bs8(0x0f), bs8(0x54), xmm, no_xmm_pref] + rmmod(rmreg, rm_arg)) -addop("andpd", [bs8(0x0f), bs8(0x54), xmm, pref_66] + rmmod(rmreg, rm_arg)) +addop("andps", [bs8(0x0f), bs8(0x54), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm)) +addop("andpd", [bs8(0x0f), bs8(0x54), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) -addop("maxsd", [bs8(0x0f), bs8(0x5f), xmm, pref_f2] + rmmod(rmreg, rm_arg)) +addop("maxsd", [bs8(0x0f), bs8(0x5f), pref_f2] + rmmod(xmm_reg, rm_arg_xmm_m64)) +addop("maxss", [bs8(0x0f), bs8(0x5f), pref_f3] + rmmod(xmm_reg, rm_arg_xmm_m32)) addop("cvtsi2sd", - [bs8(0x0f), bs8(0x2a), xmmreg, pref_f2] + rmmod(rmreg, rm_arg)) + [bs8(0x0f), bs8(0x2a), xmmreg, pref_f2] + rmmod(xmm_reg, rm_arg)) addop("cvtsi2ss", - [bs8(0x0f), bs8(0x2a), xmmreg, pref_f3] + rmmod(rmreg, rm_arg)) + [bs8(0x0f), bs8(0x2a), xmmreg, pref_f3] + rmmod(xmm_reg, rm_arg)) addop("cvttsd2ss", @@ -3724,9 +3576,6 @@ addop("cvttss2si", [bs8(0x0f), bs8(0x2c), xmmreg, pref_f3] + rmmod(rmreg, rm_arg)) -# type("movupd", (mn_x86,), {"fields":[bs8(0x0f), bs8(0x10), xmm, pref_f2] -# + rmmod(rmreg, rm_arg_sxd), 'prefixed':'\xf2'}) - addop("movzx", [bs8(0x0f), bs("1011011"), w8, sx] + rmmod(rmreg, rm_arg_sx)) addop("mul", [bs('1111011'), w8] + rmmod(d4, rm_arg_w8)) @@ -3741,9 +3590,6 @@ addop("out", [bs("1110011"), w8, u08, d_eax]) addop("out", [bs("1110111"), w8, d_edx, d_eax]) addop("outsb", [bs8(0x6e)]) -# outs_name = {16:'OUTSW', 32:'OUTSD', 64:'OUTSD'} -# bs_outs_name = bs_modname_size(l=0, name=outs_name) -# addop("outs", [bs8(0x6f), bs_outs_name]) addop("outsw", [bs8(0x6f), bs_opmode16]) addop("outsd", [bs8(0x6f), bs_opmode32]) addop("outsd", [bs8(0x6f), bs_opmode64]) @@ -3776,15 +3622,9 @@ addop("pop", [bs8(0x0f), stk, bs8(0xa1), d_fs, bs_opmode64]) addop("pop", [bs8(0x0f), stk, bs8(0xa9), d_gs, bs_opmode64]) -# popa_name = {16:'POPA', 32:'POPAD'} -# bs_popa_name = bs_modname_size(l=0, name=popa_name) -# addop("popa", [bs8(0x61), bs_popa_name]) addop("popa", [bs8(0x61), stk, bs_opmode16]) addop("popad", [bs8(0x61), stk, bs_opmode32]) -# popf_name = {16:'POPF', 32:'POPFD', 64:'POPFQ'} -# bs_popf_name = bs_modname_size(l=0, name=popf_name) -# addop("popf", [bs8(0x9d), bs_popf_name]) addop("popfw", [bs8(0x9d), stk, bs_opmode16]) addop("popfd", [bs8(0x9d), stk, bs_opmode32]) addop("popfq", [bs8(0x9d), stk, bs_opmode64]) @@ -3827,16 +3667,10 @@ addop("push", [bs8(0x06), stk, d_es, bs_opmode64]) addop("push", [bs8(0x0f), stk, bs8(0xa0), d_fs, bs_opmode64]) addop("push", [bs8(0x0f), stk, bs8(0xa8), d_gs, bs_opmode64]) -# pusha_name = {16:'PUSHA', 32:'PUSHAD'} -# bs_pusha_name = bs_modname_size(l=0, name=pusha_name) -# addop("pusha", [bs8(0x60), bs_pusha_name]) addop("pusha", [bs8(0x60), stk, bs_opmode16_no64]) addop("pushad", [bs8(0x60), stk, bs_opmode32_no64]) -# pushf_name = {16:'PUSHF', 32:'PUSHFD', 64:'PUSHFQ'} -# bs_pushf_name = bs_modname_size(l=0, name=pushf_name) -# addop("pushf", [bs8(0x9c), bs_pushf_name]) addop("pushfw", [bs8(0x9c), stk, bs_opmode16]) addop("pushfd", [bs8(0x9c), stk, bs_opmode32]) addop("pushfq", [bs8(0x9c), stk, bs_opmode64]) @@ -3874,9 +3708,6 @@ addop("sar", [bs('110100'), d_cl1, w8] + addop("sar", [bs('1100000'), w8] + rmmod(d7, rm_arg_w8) + [u08]) addop("scasb", [bs8(0xae)]) -# scas_name = {16:'SCASW', 32:'SCASD', 64:'SCASQ'} -# bs_scas_name = bs_modname_size(l=0, name=scas_name) -# addop("scas", [bs8(0xaf), bs_scas_name]) addop("scasw", [bs8(0xaf), bs_opmode16]) addop("scasd", [bs8(0xaf), bs_opmode32]) addop("scasq", [bs8(0xaf), bs_opmode64]) @@ -3910,9 +3741,6 @@ addop("stc", [bs8(0xf9)]) addop("std", [bs8(0xfd)]) addop("sti", [bs8(0xfb)]) addop("stosb", [bs8(0xaa)]) -# stos_name = {16:'STOSW', 32:'STOSD', 64:'STOSQ'} -# bs_stos_name = bs_modname_size(l=0, name=stos_name) -# addop("stos", [bs8(0xab), bs_stos_name]) addop("stosw", [bs8(0xab), bs_opmode16]) addop("stosd", [bs8(0xab), bs_opmode32]) addop("stosq", [bs8(0xab), bs_opmode64]) @@ -3957,7 +3785,7 @@ addop("xor", [bs("001100"), swapargs, w8] + addop("xgetbv", [bs8(0x0f), bs8(0x01), bs8(0xd0)]) -#addop("pand", [bs8(0x0f), bs8(0xdb), xmm, pref_66])# + rmmod(rmreg, rm_arg)) +#addop("pand", [bs8(0x0f), bs8(0xdb), pref_66])# + rmmod(rmreg, rm_arg)) #### MMX/SSE/AVX operations ####Â Categories are the same than here: https://software.intel.com/sites/landingpage/IntrinsicsGuide/ @@ -3968,88 +3796,90 @@ addop("xgetbv", [bs8(0x0f), bs8(0x01), bs8(0xd0)]) ## Move # SSE -# movaps_name = {16:'MOVAPD', 32:'MOVAPS', 64:'MOVAPS'} -# bs_movaps_name = bs_modname_size(l=0, name=movaps_name) -# addop("movaps", [bs8(0x0f), bs("0010100"), swapargs, xmm] + rmmod(rmreg, -# rm_arg) + [ bs_movaps_name], [rmreg, rm_arg]) addop("movapd", [bs8(0x0f), bs("0010100"), swapargs, xmm] - + rmmod(rmreg, rm_arg) + [bs_opmode16], [rmreg, rm_arg]) + + rmmod(xmm_reg, rm_arg_xmm) + [bs_opmode16], [xmm_reg, rm_arg_xmm]) addop("movaps", [bs8(0x0f), bs("0010100"), swapargs, xmm] - + rmmod(rmreg, rm_arg) + [bs_opmode32], [rmreg, rm_arg]) + + rmmod(xmm_reg, rm_arg_xmm) + [bs_opmode32], [xmm_reg, rm_arg_xmm]) addop("movaps", [bs8(0x0f), bs("0010100"), swapargs, xmm] - + rmmod(rmreg, rm_arg) + [bs_opmode64], [rmreg, rm_arg]) -addop("movdqu", [bs8(0x0f), bs("011"), swapargs, bs("1111"), xmm, pref_f3] - + rmmod(rmreg, rm_arg), [rmreg, rm_arg]) -addop("movdqa", [bs8(0x0f), bs("011"), swapargs, bs("1111"), xmm, pref_66] - + rmmod(rmreg, rm_arg), [rmreg, rm_arg]) + + rmmod(xmm_reg, rm_arg_xmm) + [bs_opmode64], [xmm_reg, rm_arg_xmm]) +addop("movdqu", [bs8(0x0f), bs("011"), swapargs, bs("1111"), pref_f3] + + rmmod(xmm_reg, rm_arg_xmm), [xmm_reg, rm_arg_xmm]) +addop("movdqa", [bs8(0x0f), bs("011"), swapargs, bs("1111"), pref_66] + + rmmod(xmm_reg, rm_arg_xmm), [xmm_reg, rm_arg_xmm]) ## Additions # SSE -addop("paddb", [bs8(0x0f), bs8(0xfc), xmm, pref_66] + rmmod(rmreg, rm_arg)) -addop("paddw", [bs8(0x0f), bs8(0xfd), xmm, pref_66] + rmmod(rmreg, rm_arg)) -addop("paddd", [bs8(0x0f), bs8(0xfe), xmm, pref_66] + rmmod(rmreg, rm_arg)) -addop("paddq", [bs8(0x0f), bs8(0xd4), xmm, pref_66] + rmmod(rmreg, rm_arg)) +addop("paddb", [bs8(0x0f), bs8(0xfc), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) +addop("paddw", [bs8(0x0f), bs8(0xfd), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) +addop("paddd", [bs8(0x0f), bs8(0xfe), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) +addop("paddq", [bs8(0x0f), bs8(0xd4), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) + +addop("paddb", [bs8(0x0f), bs8(0xfc), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm)) +addop("paddw", [bs8(0x0f), bs8(0xfd), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm)) +addop("paddd", [bs8(0x0f), bs8(0xfe), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm)) +addop("paddq", [bs8(0x0f), bs8(0xd4), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm)) ## Substractions # SSE -addop("psubb", [bs8(0x0f), bs8(0xf8), xmm, pref_66] + rmmod(rmreg, rm_arg)) -addop("psubw", [bs8(0x0f), bs8(0xf9), xmm, pref_66] + rmmod(rmreg, rm_arg)) -addop("psubd", [bs8(0x0f), bs8(0xfa), xmm, pref_66] + rmmod(rmreg, rm_arg)) -addop("psubq", [bs8(0x0f), bs8(0xfb), xmm, pref_66] + rmmod(rmreg, rm_arg)) +addop("psubb", [bs8(0x0f), bs8(0xf8), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) +addop("psubw", [bs8(0x0f), bs8(0xf9), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) +addop("psubd", [bs8(0x0f), bs8(0xfa), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) +addop("psubq", [bs8(0x0f), bs8(0xfb), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) + +addop("psubb", [bs8(0x0f), bs8(0xf8), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm)) +addop("psubw", [bs8(0x0f), bs8(0xf9), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm)) +addop("psubd", [bs8(0x0f), bs8(0xfa), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm)) +addop("psubq", [bs8(0x0f), bs8(0xfb), no_xmm_pref] + rmmod(mm_reg, rm_arg_mm)) ### Arithmetic (floating-point) ### ## Additions # SSE -addop("addps", [bs8(0x0f), bs8(0x58), xmm, no_xmm_pref] + rmmod(rmreg, rm_arg)) -addop("addpd", [bs8(0x0f), bs8(0x58), xmm, pref_66] + rmmod(rmreg, rm_arg)) +addop("addps", [bs8(0x0f), bs8(0x58), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm)) +addop("addpd", [bs8(0x0f), bs8(0x58), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) ## Substractions # SSE -addop("subps", [bs8(0x0f), bs8(0x5c), xmm, no_xmm_pref] + rmmod(rmreg, rm_arg)) -addop("subpd", [bs8(0x0f), bs8(0x5c), xmm, pref_66] + rmmod(rmreg, rm_arg)) +addop("subps", [bs8(0x0f), bs8(0x5c), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm)) +addop("subpd", [bs8(0x0f), bs8(0x5c), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) ## Multiplications # SSE -addop("mulps", [bs8(0x0f), bs8(0x59), xmm, no_xmm_pref] + rmmod(rmreg, rm_arg)) -addop("mulpd", [bs8(0x0f), bs8(0x59), xmm, pref_66] + rmmod(rmreg, rm_arg)) +addop("mulps", [bs8(0x0f), bs8(0x59), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm)) +addop("mulpd", [bs8(0x0f), bs8(0x59), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) ## Divisions # SSE -addop("divps", [bs8(0x0f), bs8(0x5e), xmm, no_xmm_pref] + rmmod(rmreg, rm_arg)) -addop("divpd", [bs8(0x0f), bs8(0x5e), xmm, pref_66] + rmmod(rmreg, rm_arg)) +addop("divps", [bs8(0x0f), bs8(0x5e), no_xmm_pref] + rmmod(xmm_reg, rm_arg_xmm)) +addop("divpd", [bs8(0x0f), bs8(0x5e), pref_66] + rmmod(xmm_reg, rm_arg_xmm)) ### Logical (floating-point) ### ## XOR # SSE -# xorps_name = {16:'XORPD', 32:'XORPS', 64:'XORPS'} -# bs_xorps_name = bs_modname_size(l=0, name=xorps_name) -# addop("xorps", [bs8(0x0f), bs8(0x57), xmm] + rmmod(rmreg) + [ -# bs_xorps_name] ) -addop("xorpd", [bs8(0x0f), bs8(0x57), xmm] + rmmod(rmreg) + [bs_opmode16]) -addop("xorps", [bs8(0x0f), bs8(0x57), xmm] + rmmod(rmreg) + [bs_opmode32]) -addop("xorps", [bs8(0x0f), bs8(0x57), xmm] + rmmod(rmreg) + [bs_opmode64]) +addop("xorpd", [bs8(0x0f), bs8(0x57), xmm] + rmmod(xmm_reg, rm_arg_xmm) + [bs_opmode16]) +addop("xorps", [bs8(0x0f), bs8(0x57), xmm] + rmmod(xmm_reg, rm_arg_xmm) + [bs_opmode32]) +addop("xorps", [bs8(0x0f), bs8(0x57), xmm] + rmmod(xmm_reg, rm_arg_xmm) + [bs_opmode64]) ## AND # MMX -addop("pand", [bs8(0x0f), bs8(0xdb), mm, no_xmm_pref] + - rmmod(rmreg, rm_arg), [rmreg, rm_arg]) +addop("pand", [bs8(0x0f), bs8(0xdb), no_xmm_pref] + + rmmod(mm_reg, rm_arg_mm), [mm_reg, rm_arg_mm]) # SSE -addop("pand", [bs8(0x0f), bs8(0xdb), xmm, pref_66] + - rmmod(rmreg, rm_arg), [rmreg, rm_arg]) +addop("pand", [bs8(0x0f), bs8(0xdb), pref_66] + + rmmod(xmm_reg, rm_arg_xmm), [xmm_reg, rm_arg_xmm]) ## OR # MMX -addop("por", [bs8(0x0f), bs8(0xeb), mm, no_xmm_pref] + - rmmod(rmreg, rm_arg), [rmreg, rm_arg]) +addop("por", [bs8(0x0f), bs8(0xeb), no_xmm_pref] + + rmmod(mm_reg, rm_arg_mm), [mm_reg, rm_arg_mm]) # SSE -addop("por", [bs8(0x0f), bs8(0xeb), xmm, pref_66] + - rmmod(rmreg, rm_arg), [rmreg, rm_arg]) +addop("por", [bs8(0x0f), bs8(0xeb), pref_66] + + rmmod(xmm_reg, rm_arg_xmm), [xmm_reg, rm_arg_xmm]) ### Convert ### SS = single precision @@ -4060,15 +3890,15 @@ addop("por", [bs8(0x0f), bs8(0xeb), xmm, pref_66] + ## # SSE -addop("cvtss2sd", [bs8(0x0f), bs8(0x5a), xmm, pref_f3] - + rmmod(rmreg, rm_arg)) +addop("cvtss2sd", [bs8(0x0f), bs8(0x5a), pref_f3] + + rmmod(xmm_reg, rm_arg_xmm_m32)) ## SD -> SS ## # SSE -addop("cvtsd2ss", [bs8(0x0f), bs8(0x5a), xmm, pref_f2] - + rmmod(rmreg, rm_arg)) +addop("cvtsd2ss", [bs8(0x0f), bs8(0x5a), pref_f2] + + rmmod(xmm_reg, rm_arg_xmm_m64)) mn_x86.bintree = factor_one_bit(mn_x86.bintree) diff --git a/test/arch/aarch64/arch.py b/test/arch/aarch64/arch.py new file mode 100644 index 00000000..a42fd9db --- /dev/null +++ b/test/arch/aarch64/arch.py @@ -0,0 +1,1786 @@ +import os, sys +import time +from miasm2.arch.aarch64.arch import * + +filename = os.environ.get('PYTHONSTARTUP') +if filename and os.path.isfile(filename): + execfile(filename) + + +reg_tests_aarch64 = [ + ("XXXXXXXX TST W5, W3", + "BF00036A"), + ("XXXXXXXX LDP X19, X20, [SP, 0x10]", + "F35341A9"), + ("XXXXXXXX STP X24, X23, [SP, 0x10]", + "F85F01A9"), + + + ("004024DC MVN X1, X0", + "E10320AA"), + + ("00011374 SUB SP, SP, 0x20", + "FF8300D1"), + ("0009F254 SUB W19, W19, 0x40", + "73020151"), + ("00025F24 SUBS W3, W0, 0x1", + "03040071"), + ("00071338 SUBS X1, X1, 0x1", + "210400F1"), + ("0000E678 SUB SP, SP, 0x360", + "FF830DD1"), + ("0000E7E4 ADD X0, X24, 0x40", + "00030191"), + ("00011230 ADDS X19, X19, 0x8", + "732200B1"), + ("0000CC68 ADRP X3, 0xCF000", + "630600F0"), + ("000432A0 ADR X1, 0xC", + "61000010"), + ("0000E928 SUB X22, X22, X2", + "D60202CB"), + ("00035B50 SUB W2, W0, W1", + "0200014B"), + ("00012018 ADD X0, X0, X3 LSL 0x1", + "0004038B"), + ("0000E9A4 SUBS W23, W2, W23", + "5700176B"), + ("0006D500 ADD X0, X0, 0x1000", + "00044091"), + ("000A57C0 ADD X0, X0, 0x5000", + "00144091"), + ("0001EDF4 ADD W0, W0, W2 LSR 0x1", + "0004420B"), + ("00067434 ADD X19, X0, X19 LSR 0x3", + "130C538B"), + ("0008E148 SUB W20, W1, W20 ASR 0x1", + "3404944B"), + ("00013258 SUB X19, X1, X19 ASR 0x3F", + "33FC93CB"), + ("0000D66C SUB SP, X23, X0 UXTX 0x0", + "FF6220CB"), + ("00071EF4 SUBS X0, X0, 0x10000", + "004040F1"), + ("0000D5AC NEG W6, W6", + "E603064B"), + + + ("004028B8 CMP X0, XZR", + "1F001FEB"), + ("004029D0 CMP X0, 0x3F", + "1FFC00F1"), + + + ("0007FA38 AND W0, W0, 0x7000000", + "00080812"), + + ("0009E5C4 AND W0, W0, 0xFF", + "001C0012"), + ("0007BDB0 AND W0, W0, 0x7", + "00080012"), + + ("000A0A14 EOR W24, W24, 0x6", + "18071F52"), + + ("0004A0C0 EOR W19, W0, 0x3", + "13040052"), + + ("00010234 EOR W0, W0, 0x4000", + "00001252"), + + ("00020924 EOR W0, W0, 0x4", + "00001E52"), + + ("0002094C EOR W0, W0, 0x8", + "00001D52"), + ("0004B410 EOR W0, W0, 0x1", + "00000052"), + + + ("000466BC AND X19, X0, 0xFFFFFFFFFFFFFFF8", + "13F07D92"), + ("0000FA3C AND W0, W0, 0xFF00", + "001C1812"), + ("0002049C AND W1, W0, 0x7FFF", + "01380012"), + ("0001F650 AND X0, X0, 0x1FFFFFFF0", + "00707C92"), + ("0009B4B0 AND W0, W0, 0xFFFFFF87", + "006C1912"), + ("0005D7D4 AND W0, W0, 0xFF0000FF", + "003C0812"), + ("0000D564 ORR W0, W0, 0xFFFFFFF8", + "00701D32"), + ("00065E24 ORR X19, X19, 0x1", + "730240B2"), + ("000165AC ANDS W0, W24, 0xE", + "000B1F72"), + ("00079A80 ANDS X20, X2, 0xFF", + "541C40F2"), + + ("0005BD5C AND W0, W0, W24", + "0000180A"), + ("0008F824 AND W0, W24, W23", + "0003170A"), + ("0001AFE4 BIC X5, X23, X5", + "E502258A"), + + ("000A36B4 BIC W0, W21, W19", + "A002330A"), + ("0000CD54 ORR W0, W2, W0 LSL 0x10", + "4040002A"), + ("0000CD88 ORR X0, X0, X1 LSL 0x20", + "008001AA"), + ("0001C420 ORR X21, X21, X0 LSL 0x30", + "B5C200AA"), + ("0006C060 ORR W1, W5, W1 ASR 0x8", + "A120812A"), + ("0002962C ORN W0, W0, W25", + "0000392A"), + ("0000FBE4 EOR W1, W1, W0", + "2100004A"), + ("0001C3B0 EOR X3, X2, X2 ASR 0x3F", + "43FC82CA"), + ("00022174 EOR W3, W3, W1 LSL 0x8", + "6320014A"), + ("00010B0C ANDS W19, W19, W1", + "7302016A"), + ("0006634C ANDS X2, X20, X2", + "820202EA"), + ("0003E0C8 BICS W19, W19, W2", + "7302226A"), + + ("00026388 MOVK W0, 0x4550 LSL 0x10", + "00AAA872"), + ("000218A4 MOVZ W0, 0x2580", + "00B08452"), + ("000340E8 MOVZ X1, 0x0", + "010080D2"), + ("0001D628 MOVZ X1, 0x100000", + "0102A0D2"), + ("0003317C MOVN W2, 0x0", + "02008012"), + ("00034FC0 MOVN W2, 0x80000000", + "0200B012"), + ("000234C8 MOVN X2, 0x8000000000000000", + "0200F092"), + ("000290B0 MOVN X3, 0x0", + "03008092"), + + ("00029074 MOV X0, X26", + "E0031AAA"), + ("00028F40 MOV W0, W24", + "E003182A"), + ("00028D84 B.NE 0x40", + "01020054"), + ("00028DC0 B.GE 0xC", + "6A000054"), + ("0000C880 B.NE 0xFFFFFFFFFFFFFFD8", + "C1FEFF54"), + ("0000D27C B.LS 0x2C", + "69010054"), + + ("XXXXXXXX ADD W0, W0, W0 UXTB 0x3", + "000C200B"), + ("XXXXXXXX ADD W0, W0, W0 UXTB 0x1", + "0004200B"), + ("XXXXXXXX ADD W0, W0, W0 UXTB 0x0", + "0000200B"), + ("0000B330 BR X17", + "20021FD6"), + ("000A54F0 BLR X20", + "80023FD6"), + ("000A5684 RET LR", + "C0035FD6"), + ("000A563C BL 0xFFFFFFFFFFF66A54", + "959AFD97"), + ("000A4CF4 B 0xFFFFFFFFFFFFFFD0", + "F4FFFF17"), + + ("00012008 STRB W7, [X6], 0x2", + "C7240038"), + ("00010A2C LDRB W1, [X19], 0x1", + "61164038"), + ("0002FDF0 LDR W0, [X24], 0x4", + "004740B8"), + ("000A8F38 STR W2, [X1], 0x4", + "224400B8"), + ("0003F2D0 STR X0, [X1], 0x8", + "208400F8"), + ("00081764 LDRSB W1, [X19], 0x1", + "6116C038"), + ("0002CABC STRH W1, [X0], 0x2", + "01240078"), + ("00037EF0 LDRH W2, [X1], 0x4", + "22444078"), + + ("00081504 LDR Q0, [X1], 0x10", + "2004C13C"), + ("00081508 STR B0, [X1], 0x10", + "2004013C"), + ("0008150C LDR B0, [X1], 0x10", + "2004413C"), + ("00081510 STR Q0, [X1], 0x10", + "2004813C"), + ("00081508 STR S0, [X1], 0x10", + "200401BC"), + + + ("0006A108 LDR X0, [X24, 0x8]!", + "008F40F8"), + ("0007D490 LDRB W1, [X0, 0x1]!", + "011C4038"), + ("00028888 LDRB W1, [X24, 0xFFFFFFFFFFFFFFFF]!", + "01FF5F38"), + ("0000F550 STRB W27, [X0, 0xFFFFFFFFFFFFFFFF]!", + "1BFC1F38"), + ("0001104C STR W0, [X1, 0xFFFFFFFFFFFFFFFC]!", + "20CC1FB8"), + ("00016BF0 STR WZR, [X20, 0xFFFFFFFFFFFFFFFC]!", + "9FCE1FB8"), + ("000169BC STR XZR, [X2, 0xFFFFFFFFFFFFFFF8]!", + "5F8C1FF8"), + + ("000169CC STR X2, [SP, 0x48]", + "E22700F9"), + ("000169C8 STR X2, [SP, 0x40]", + "E22300F9"), + ("0007C144 LDR W0, [X0, 0x4]", + "000440B9"), + ("0006C158 LDR W6, [X2, 0x1DD8]", + "46D85DB9"), + ("00017F04 STR XZR, [SP, 0xA8]", + "FF5700F9"), + ("00061B04 LDR X20, [X0, 0xC30]", + "141846F9"), + + + ("0000F55C STURB W19, [X24, 0xFFFFFFFFFFFFFFFF]", + "13F31F38"), + ("0000FCC4 STUR X4, [X25, 0xFFFFFFFFFFFFFFF8]", + "24831FF8"), + ("00029C40 STUR W22, [X20, 0x1A]", + "96A201B8"), + ("00036364 STURB WZR, [X20, 0xFFFFFFFFFFFFFFFF]", + "9FF21F38"), + ("0003CEF0 STURH W2, [X0, 0xFFFFFFFFFFFFFFFE]", + "02E01F78"), + ("0000E91C LDUR X2, [X1, 0xFFFFFFFFFFFFFF80]", + "220058F8"), + ("00010318 LDUR W0, [X0, 0xFFFFFFFFFFFFFFF0]", + "00005FB8"), + ("0000F54C LDURB W19, [X24, 0xFFFFFFFFFFFFFFFF]", + "13F35F38"), + ("0006D484 LDURH W4, [X3, 0xFFFFFFFFFFFFFFFE]", + "64E05F78"), + ("000A028C LDURSH W3, [X3, 0xFFFFFFFFFFFFFFFE]", + "63E0DF78"), + + ("0000C6E8 STTRB W7, [X5, 0xF]", + "A7F80038"), + ("0000C6F8 LDTRB W7, [X5, 0xF]", + "A7F84038"), + ("0000C700 LDURSB X7, [X5, 0xF]", + "A7F08038"), + ("0000C708 LDTRSB X7, [X5, 0xF]", + "A7F88038"), + ("0000C728 STTR B7, [X5, 0xF]", + "A7F8003C"), + ("0000C738 LDTR B7, [X5, 0xF]", + "A7F8403C"), + ("0000C740 STUR Q7, [X5, 0xF]", + "A7F0803C"), + + + + + + + + + +# brute force + ("0000C6E0 ADD W7, W5, 0xF", + "A73C0011"), + ("0000C6E4 ADD W7, W5, 0xF000", + "A73C4011"), + ("0000C6E8 ADDS W7, W5, 0xF", + "A73C0031"), + ("0000C6EC ADDS W7, W5, 0xF000", + "A73C4031"), + ("0000C6F0 SUB W7, W5, 0xF", + "A73C0051"), + ("0000C6F4 SUB W7, W5, 0xF000", + "A73C4051"), + ("0000C6F8 SUBS W7, W5, 0xF", + "A73C0071"), + ("0000C6FC SUBS W7, W5, 0xF000", + "A73C4071"), + ("0000C700 ADD X7, X5, 0xF", + "A73C0091"), + ("0000C704 ADD X7, X5, 0xF000", + "A73C4091"), + ("0000C708 ADDS X7, X5, 0xF", + "A73C00B1"), + ("0000C70C ADDS X7, X5, 0xF000", + "A73C40B1"), + ("0000C710 SUB X7, X5, 0xF", + "A73C00D1"), + ("0000C714 SUB X7, X5, 0xF000", + "A73C40D1"), + ("0000C718 SUBS X7, X5, 0xF", + "A73C00F1"), + ("0000C71C SUBS X7, X5, 0xF000", + "A73C40F1"), + + ("0000C6E0 ADD W15, W7, W5 LSL 0xF", + "EF3C050B"), + ("0000C6E4 ADD W15, W7, W5 LSR 0xF", + "EF3C450B"), + ("0000C6E8 ADDS W15, W7, W5 LSL 0xF", + "EF3C052B"), + ("0000C6EC ADDS W15, W7, W5 LSR 0xF", + "EF3C452B"), + ("0000C6F0 SUB W15, W7, W5 LSL 0xF", + "EF3C054B"), + ("0000C6F4 SUB W15, W7, W5 LSR 0xF", + "EF3C454B"), + ("0000C6F8 SUBS W15, W7, W5 LSL 0xF", + "EF3C056B"), + ("0000C6FC SUBS W15, W7, W5 LSR 0xF", + "EF3C456B"), + ("0000C700 ADD X15, X7, X5 LSL 0xF", + "EF3C058B"), + ("0000C704 ADD X15, X7, X5 LSR 0xF", + "EF3C458B"), + ("0000C708 ADDS X15, X7, X5 LSL 0xF", + "EF3C05AB"), + ("0000C70C ADDS X15, X7, X5 LSR 0xF", + "EF3C45AB"), + ("0000C710 SUB X15, X7, X5 LSL 0xF", + "EF3C05CB"), + ("0000C714 SUB X15, X7, X5 LSR 0xF", + "EF3C45CB"), + ("0000C718 SUBS X15, X7, X5 LSL 0xF", + "EF3C05EB"), + ("0000C71C SUBS X15, X7, X5 LSR 0xF", + "EF3C45EB"), + + + ("0000C6E0 ADD W3, W15, W7 UXTB 0x3", + "E30D270B"), + ("0000C6E4 ADD W3, W15, W7 UXTH 0x3", + "E32D270B"), + ("0000C6E8 ADD W3, W15, W7 UXTW 0x3", + "E34D270B"), + ("0000C6EC ADD W3, W15, W7 UXTX 0x3", + "E36D270B"), + ("0000C6F0 ADD W3, W15, W7 SXTB 0x3", + "E38D270B"), + ("0000C6F4 ADD W3, W15, W7 SXTH 0x3", + "E3AD270B"), + ("0000C6F8 ADD W3, W15, W7 SXTW 0x3", + "E3CD270B"), + ("0000C6FC ADD W3, W15, W7 SXTX 0x3", + "E3ED270B"), + ("0000C700 ADDS W3, W15, W7 UXTB 0x3", + "E30D272B"), + ("0000C704 ADDS W3, W15, W7 UXTH 0x3", + "E32D272B"), + ("0000C708 ADDS W3, W15, W7 UXTW 0x3", + "E34D272B"), + ("0000C70C ADDS W3, W15, W7 UXTX 0x3", + "E36D272B"), + ("0000C710 ADDS W3, W15, W7 SXTB 0x3", + "E38D272B"), + ("0000C714 ADDS W3, W15, W7 SXTH 0x3", + "E3AD272B"), + ("0000C718 ADDS W3, W15, W7 SXTW 0x3", + "E3CD272B"), + ("0000C71C ADDS W3, W15, W7 SXTX 0x3", + "E3ED272B"), + ("0000C720 SUB W3, W15, W7 UXTB 0x3", + "E30D274B"), + ("0000C724 SUB W3, W15, W7 UXTH 0x3", + "E32D274B"), + ("0000C728 SUB W3, W15, W7 UXTW 0x3", + "E34D274B"), + ("0000C72C SUB W3, W15, W7 UXTX 0x3", + "E36D274B"), + ("0000C730 SUB W3, W15, W7 SXTB 0x3", + "E38D274B"), + ("0000C734 SUB W3, W15, W7 SXTH 0x3", + "E3AD274B"), + ("0000C738 SUB W3, W15, W7 SXTW 0x3", + "E3CD274B"), + ("0000C73C SUB W3, W15, W7 SXTX 0x3", + "E3ED274B"), + ("0000C740 SUBS W3, W15, W7 UXTB 0x3", + "E30D276B"), + ("0000C744 SUBS W3, W15, W7 UXTH 0x3", + "E32D276B"), + ("0000C748 SUBS W3, W15, W7 UXTW 0x3", + "E34D276B"), + ("0000C74C SUBS W3, W15, W7 UXTX 0x3", + "E36D276B"), + ("0000C750 SUBS W3, W15, W7 SXTB 0x3", + "E38D276B"), + ("0000C754 SUBS W3, W15, W7 SXTH 0x3", + "E3AD276B"), + ("0000C758 SUBS W3, W15, W7 SXTW 0x3", + "E3CD276B"), + ("0000C75C SUBS W3, W15, W7 SXTX 0x3", + "E3ED276B"), + ("0000C760 ADD X3, X15, W7 UXTB 0x3", + "E30D278B"), + ("0000C764 ADD X3, X15, W7 UXTH 0x3", + "E32D278B"), + ("0000C768 ADD X3, X15, W7 UXTW 0x3", + "E34D278B"), + ("0000C76C ADD X3, X15, X7 UXTX 0x3", + "E36D278B"), + ("0000C770 ADD X3, X15, W7 SXTB 0x3", + "E38D278B"), + ("0000C774 ADD X3, X15, W7 SXTH 0x3", + "E3AD278B"), + ("0000C778 ADD X3, X15, W7 SXTW 0x3", + "E3CD278B"), + ("0000C77C ADD X3, X15, X7 SXTX 0x3", + "E3ED278B"), + ("0000C780 ADDS X3, X15, W7 UXTB 0x3", + "E30D27AB"), + ("0000C784 ADDS X3, X15, W7 UXTH 0x3", + "E32D27AB"), + ("0000C788 ADDS X3, X15, W7 UXTW 0x3", + "E34D27AB"), + ("0000C78C ADDS X3, X15, X7 UXTX 0x3", + "E36D27AB"), + ("0000C790 ADDS X3, X15, W7 SXTB 0x3", + "E38D27AB"), + ("0000C794 ADDS X3, X15, W7 SXTH 0x3", + "E3AD27AB"), + ("0000C798 ADDS X3, X15, W7 SXTW 0x3", + "E3CD27AB"), + ("0000C79C ADDS X3, X15, X7 SXTX 0x3", + "E3ED27AB"), + ("0000C7A0 SUB X3, X15, W7 UXTB 0x3", + "E30D27CB"), + ("0000C7A4 SUB X3, X15, W7 UXTH 0x3", + "E32D27CB"), + ("0000C7A8 SUB X3, X15, W7 UXTW 0x3", + "E34D27CB"), + ("0000C7AC SUB X3, X15, X7 UXTX 0x3", + "E36D27CB"), + ("0000C7B0 SUB X3, X15, W7 SXTB 0x3", + "E38D27CB"), + ("0000C7B4 SUB X3, X15, W7 SXTH 0x3", + "E3AD27CB"), + ("0000C7B8 SUB X3, X15, W7 SXTW 0x3", + "E3CD27CB"), + ("0000C7BC SUB X3, X15, X7 SXTX 0x3", + "E3ED27CB"), + ("0000C7C0 SUBS X3, X15, W7 UXTB 0x3", + "E30D27EB"), + ("0000C7C4 SUBS X3, X15, W7 UXTH 0x3", + "E32D27EB"), + ("0000C7C8 SUBS X3, X15, W7 UXTW 0x3", + "E34D27EB"), + ("0000C7CC SUBS X3, X15, X7 UXTX 0x3", + "E36D27EB"), + ("0000C7D0 SUBS X3, X15, W7 SXTB 0x3", + "E38D27EB"), + ("0000C7D4 SUBS X3, X15, W7 SXTH 0x3", + "E3AD27EB"), + ("0000C7D8 SUBS X3, X15, W7 SXTW 0x3", + "E3CD27EB"), + ("0000C7DC SUBS X3, X15, X7 SXTX 0x3", + "E3ED27EB"), + + + ("0000C6E0 AND W3, W15, 0xFE000001", + "E31D0712"), + ("0000C6E4 ORR W3, W15, 0xFE000001", + "E31D0732"), + ("0000C6E8 EOR W3, W15, 0xFE000001", + "E31D0752"), + ("0000C6EC ANDS W3, W15, 0xFE000001", + "E31D0772"), +# XXX???? TODO CHECK +# ("0000C6F0 AND X3, X15, 0xFE000001FE000001", +# "E31D0792"), +# ("0000C6F4 ORR X3, X15, 0xFE000001FE000001", +# "E31D07B2"), +# ("0000C6F8 EOR X3, X15, 0xFE000001FE000001", +# "E31D07D2"), +# ("0000C6FC ANDS X3, X15, 0xFE000001FE000001", +# "E31D07F2"), + + + ("0000C6E0 AND W3, W15, W7 LSL 0xB", + "E32D070A"), + ("0000C6E4 BIC W3, W15, W7 LSL 0xB", + "E32D270A"), + ("0000C6E8 AND W3, W15, W7 LSR 0xB", + "E32D470A"), + ("0000C6EC BIC W3, W15, W7 LSR 0xB", + "E32D670A"), + ("0000C6F0 AND W3, W15, W7 ASR 0xB", + "E32D870A"), + ("0000C6F4 BIC W3, W15, W7 ASR 0xB", + "E32DA70A"), + ("0000C6F8 AND W3, W15, W7 ROR 0xB", + "E32DC70A"), + ("0000C6FC BIC W3, W15, W7 ROR 0xB", + "E32DE70A"), + ("0000C700 ORR W3, W15, W7 LSL 0xB", + "E32D072A"), + ("0000C704 ORN W3, W15, W7 LSL 0xB", + "E32D272A"), + ("0000C708 ORR W3, W15, W7 LSR 0xB", + "E32D472A"), + ("0000C70C ORN W3, W15, W7 LSR 0xB", + "E32D672A"), + ("0000C710 ORR W3, W15, W7 ASR 0xB", + "E32D872A"), + ("0000C714 ORN W3, W15, W7 ASR 0xB", + "E32DA72A"), + ("0000C718 ORR W3, W15, W7 ROR 0xB", + "E32DC72A"), + ("0000C71C ORN W3, W15, W7 ROR 0xB", + "E32DE72A"), + ("0000C720 EOR W3, W15, W7 LSL 0xB", + "E32D074A"), + ("0000C724 EON W3, W15, W7 LSL 0xB", + "E32D274A"), + ("0000C728 EOR W3, W15, W7 LSR 0xB", + "E32D474A"), + ("0000C72C EON W3, W15, W7 LSR 0xB", + "E32D674A"), + ("0000C730 EOR W3, W15, W7 ASR 0xB", + "E32D874A"), + ("0000C734 EON W3, W15, W7 ASR 0xB", + "E32DA74A"), + ("0000C738 EOR W3, W15, W7 ROR 0xB", + "E32DC74A"), + ("0000C73C EON W3, W15, W7 ROR 0xB", + "E32DE74A"), + ("0000C740 ANDS W3, W15, W7 LSL 0xB", + "E32D076A"), + ("0000C744 BICS W3, W15, W7 LSL 0xB", + "E32D276A"), + ("0000C748 ANDS W3, W15, W7 LSR 0xB", + "E32D476A"), + ("0000C74C BICS W3, W15, W7 LSR 0xB", + "E32D676A"), + ("0000C750 ANDS W3, W15, W7 ASR 0xB", + "E32D876A"), + ("0000C754 BICS W3, W15, W7 ASR 0xB", + "E32DA76A"), + ("0000C758 ANDS W3, W15, W7 ROR 0xB", + "E32DC76A"), + ("0000C75C BICS W3, W15, W7 ROR 0xB", + "E32DE76A"), + ("0000C760 AND X3, X15, X7 LSL 0xB", + "E32D078A"), + ("0000C764 BIC X3, X15, X7 LSL 0xB", + "E32D278A"), + ("0000C768 AND X3, X15, X7 LSR 0xB", + "E32D478A"), + ("0000C76C BIC X3, X15, X7 LSR 0xB", + "E32D678A"), + ("0000C770 AND X3, X15, X7 ASR 0xB", + "E32D878A"), + ("0000C774 BIC X3, X15, X7 ASR 0xB", + "E32DA78A"), + ("0000C778 AND X3, X15, X7 ROR 0xB", + "E32DC78A"), + ("0000C77C BIC X3, X15, X7 ROR 0xB", + "E32DE78A"), + ("0000C780 ORR X3, X15, X7 LSL 0xB", + "E32D07AA"), + ("0000C784 ORN X3, X15, X7 LSL 0xB", + "E32D27AA"), + ("0000C788 ORR X3, X15, X7 LSR 0xB", + "E32D47AA"), + ("0000C78C ORN X3, X15, X7 LSR 0xB", + "E32D67AA"), + ("0000C790 ORR X3, X15, X7 ASR 0xB", + "E32D87AA"), + ("0000C794 ORN X3, X15, X7 ASR 0xB", + "E32DA7AA"), + ("0000C798 ORR X3, X15, X7 ROR 0xB", + "E32DC7AA"), + ("0000C79C ORN X3, X15, X7 ROR 0xB", + "E32DE7AA"), + ("0000C7A0 EOR X3, X15, X7 LSL 0xB", + "E32D07CA"), + ("0000C7A4 EON X3, X15, X7 LSL 0xB", + "E32D27CA"), + ("0000C7A8 EOR X3, X15, X7 LSR 0xB", + "E32D47CA"), + ("0000C7AC EON X3, X15, X7 LSR 0xB", + "E32D67CA"), + ("0000C7B0 EOR X3, X15, X7 ASR 0xB", + "E32D87CA"), + ("0000C7B4 EON X3, X15, X7 ASR 0xB", + "E32DA7CA"), + ("0000C7B8 EOR X3, X15, X7 ROR 0xB", + "E32DC7CA"), + ("0000C7BC EON X3, X15, X7 ROR 0xB", + "E32DE7CA"), + ("0000C7C0 ANDS X3, X15, X7 LSL 0xB", + "E32D07EA"), + ("0000C7C4 BICS X3, X15, X7 LSL 0xB", + "E32D27EA"), + ("0000C7C8 ANDS X3, X15, X7 LSR 0xB", + "E32D47EA"), + ("0000C7CC BICS X3, X15, X7 LSR 0xB", + "E32D67EA"), + ("0000C7D0 ANDS X3, X15, X7 ASR 0xB", + "E32D87EA"), + ("0000C7D4 BICS X3, X15, X7 ASR 0xB", + "E32DA7EA"), + ("0000C7D8 ANDS X3, X15, X7 ROR 0xB", + "E32DC7EA"), + ("0000C7DC BICS X3, X15, X7 ROR 0xB", + "E32DE7EA"), + + + + + ("0000C6E0 STURB W7, [X5, 0xF]", + "A7F00038"), + ("0000C6E4 STRB W7, [X5], 0xF", + "A7F40038"), + ("0000C6E8 STTRB W7, [X5, 0xF]", + "A7F80038"), + ("0000C6EC STRB W7, [X5, 0xF]!", + "A7FC0038"), + ("0000C6F0 LDURB W7, [X5, 0xF]", + "A7F04038"), + ("0000C6F4 LDRB W7, [X5], 0xF", + "A7F44038"), + ("0000C6F8 LDTRB W7, [X5, 0xF]", + "A7F84038"), + ("0000C6FC LDRB W7, [X5, 0xF]!", + "A7FC4038"), + ("0000C700 LDURSB X7, [X5, 0xF]", + "A7F08038"), + ("0000C704 LDRSB X7, [X5], 0xF", + "A7F48038"), + ("0000C708 LDTRSB X7, [X5, 0xF]", + "A7F88038"), + ("0000C70C LDRSB X7, [X5, 0xF]!", + "A7FC8038"), + ("0000C710 LDURSB W7, [X5, 0xF]", + "A7F0C038"), + ("0000C714 LDRSB W7, [X5], 0xF", + "A7F4C038"), + ("0000C718 LDTRSB W7, [X5, 0xF]", + "A7F8C038"), + ("0000C71C LDRSB W7, [X5, 0xF]!", + "A7FCC038"), + ("0000C720 STUR B7, [X5, 0xF]", + "A7F0003C"), + ("0000C724 STR B7, [X5], 0xF", + "A7F4003C"), + ("0000C728 STTR B7, [X5, 0xF]", + "A7F8003C"), + ("0000C72C STR B7, [X5, 0xF]!", + "A7FC003C"), + ("0000C730 LDUR B7, [X5, 0xF]", + "A7F0403C"), + ("0000C734 LDR B7, [X5], 0xF", + "A7F4403C"), + ("0000C738 LDTR B7, [X5, 0xF]", + "A7F8403C"), + ("0000C73C LDR B7, [X5, 0xF]!", + "A7FC403C"), + ("0000C740 STUR Q7, [X5, 0xF]", + "A7F0803C"), + ("0000C744 STR Q7, [X5], 0xF", + "A7F4803C"), + ("0000C748 STTR Q7, [X5, 0xF]", + "A7F8803C"), + ("0000C74C STR Q7, [X5, 0xF]!", + "A7FC803C"), + ("0000C750 LDUR Q7, [X5, 0xF]", + "A7F0C03C"), + ("0000C754 LDR Q7, [X5], 0xF", + "A7F4C03C"), + ("0000C758 LDTR Q7, [X5, 0xF]", + "A7F8C03C"), + ("0000C75C LDR Q7, [X5, 0xF]!", + "A7FCC03C"), + ("0000C760 STURH W7, [X5, 0xF]", + "A7F00078"), + ("0000C764 STRH W7, [X5], 0xF", + "A7F40078"), + ("0000C768 STTRH W7, [X5, 0xF]", + "A7F80078"), + ("0000C76C STRH W7, [X5, 0xF]!", + "A7FC0078"), + ("0000C770 LDURH W7, [X5, 0xF]", + "A7F04078"), + ("0000C774 LDRH W7, [X5], 0xF", + "A7F44078"), + ("0000C778 LDTRH W7, [X5, 0xF]", + "A7F84078"), + ("0000C77C LDRH W7, [X5, 0xF]!", + "A7FC4078"), + ("0000C780 LDURSH X7, [X5, 0xF]", + "A7F08078"), + ("0000C784 LDRSH X7, [X5], 0xF", + "A7F48078"), + ("0000C788 LDTRSH X7, [X5, 0xF]", + "A7F88078"), + ("0000C78C LDRSH X7, [X5, 0xF]!", + "A7FC8078"), + ("0000C790 LDURSH W7, [X5, 0xF]", + "A7F0C078"), + ("0000C794 LDRSH W7, [X5], 0xF", + "A7F4C078"), + ("0000C798 LDTRSH W7, [X5, 0xF]", + "A7F8C078"), + ("0000C79C LDRSH W7, [X5, 0xF]!", + "A7FCC078"), + ("0000C7A0 STUR H7, [X5, 0xF]", + "A7F0007C"), + ("0000C7A4 STR H7, [X5], 0xF", + "A7F4007C"), + ("0000C7A8 STTR H7, [X5, 0xF]", + "A7F8007C"), + ("0000C7AC STR H7, [X5, 0xF]!", + "A7FC007C"), + ("0000C7B0 LDUR H7, [X5, 0xF]", + "A7F0407C"), + ("0000C7B4 LDR H7, [X5], 0xF", + "A7F4407C"), + ("0000C7B8 LDTR H7, [X5, 0xF]", + "A7F8407C"), + ("0000C7BC LDR H7, [X5, 0xF]!", + "A7FC407C"), + ("0000C7E0 STUR W7, [X5, 0xF]", + "A7F000B8"), + ("0000C7E4 STR W7, [X5], 0xF", + "A7F400B8"), + ("0000C7E8 STTR W7, [X5, 0xF]", + "A7F800B8"), + ("0000C7EC STR W7, [X5, 0xF]!", + "A7FC00B8"), + ("0000C7F0 LDUR W7, [X5, 0xF]", + "A7F040B8"), + ("0000C7F4 LDR W7, [X5], 0xF", + "A7F440B8"), + ("0000C7F8 LDTR W7, [X5, 0xF]", + "A7F840B8"), + ("0000C7FC LDR W7, [X5, 0xF]!", + "A7FC40B8"), + ("0000C800 LDURSW X7, [X5, 0xF]", + "A7F080B8"), + ("0000C804 LDRSW X7, [X5], 0xF", + "A7F480B8"), + ("0000C808 LDTRSW X7, [X5, 0xF]", + "A7F880B8"), + ("0000C80C LDRSW X7, [X5, 0xF]!", + "A7FC80B8"), + ("0000C820 STUR S7, [X5, 0xF]", + "A7F000BC"), + ("0000C824 STR S7, [X5], 0xF", + "A7F400BC"), + ("0000C828 STTR S7, [X5, 0xF]", + "A7F800BC"), + ("0000C82C STR S7, [X5, 0xF]!", + "A7FC00BC"), + ("0000C830 LDUR S7, [X5, 0xF]", + "A7F040BC"), + ("0000C834 LDR S7, [X5], 0xF", + "A7F440BC"), + ("0000C838 LDTR S7, [X5, 0xF]", + "A7F840BC"), + ("0000C83C LDR S7, [X5, 0xF]!", + "A7FC40BC"), + ("0000C860 STUR X7, [X5, 0xF]", + "A7F000F8"), + ("0000C864 STR X7, [X5], 0xF", + "A7F400F8"), + ("0000C868 STTR X7, [X5, 0xF]", + "A7F800F8"), + ("0000C86C STR X7, [X5, 0xF]!", + "A7FC00F8"), + ("0000C870 LDUR X7, [X5, 0xF]", + "A7F040F8"), + ("0000C874 LDR X7, [X5], 0xF", + "A7F440F8"), + ("0000C878 LDTR X7, [X5, 0xF]", + "A7F840F8"), + ("0000C87C LDR X7, [X5, 0xF]!", + "A7FC40F8"), + ("0000C8A0 STUR D7, [X5, 0xF]", + "A7F000FC"), + ("0000C8A4 STR D7, [X5], 0xF", + "A7F400FC"), + ("0000C8A8 STTR D7, [X5, 0xF]", + "A7F800FC"), + ("0000C8AC STR D7, [X5, 0xF]!", + "A7FC00FC"), + ("0000C8B0 LDUR D7, [X5, 0xF]", + "A7F040FC"), + ("0000C8B4 LDR D7, [X5], 0xF", + "A7F440FC"), + ("0000C8B8 LDTR D7, [X5, 0xF]", + "A7F840FC"), + ("0000C8BC LDR D7, [X5, 0xF]!", + "A7FC40FC"), + ("0000C8E0 STRB W7, [X7]", + "E7000039"), + ("0000C8E4 LDRB W7, [X7]", + "E7004039"), + ("0000C8E8 LDRSB X7, [X7]", + "E7008039"), + ("0000C8EC LDRSB W7, [X7]", + "E700C039"), + ("0000C8F0 STR B7, [X7]", + "E700003D"), + ("0000C8F4 LDR B7, [X7]", + "E700403D"), + ("0000C8F8 STR Q7, [X7]", + "E700803D"), + ("0000C8FC LDR Q7, [X7]", + "E700C03D"), + ("0000C900 STRH W7, [X7]", + "E7000079"), + ("0000C904 LDRH W7, [X7]", + "E7004079"), + ("0000C908 LDRSH X7, [X7]", + "E7008079"), + ("0000C90C LDRSH W7, [X7]", + "E700C079"), + ("0000C910 STR H7, [X7]", + "E700007D"), + ("0000C914 LDR H7, [X7]", + "E700407D"), + ("0000C920 STR W7, [X7]", + "E70000B9"), + ("0000C924 LDR W7, [X7]", + "E70040B9"), + ("0000C928 LDRSW X7, [X7]", + "E70080B9"), + ("0000C930 STR S7, [X7]", + "E70000BD"), + ("0000C934 LDR S7, [X7]", + "E70040BD"), + ("0000C940 STR X7, [X7]", + "E70000F9"), + ("0000C944 LDR X7, [X7]", + "E70040F9"), + ("0000C950 STR D7, [X7]", + "E70000FD"), + ("0000C954 LDR D7, [X7]", + "E70040FD"), + + ("0000C6E0 STRB W17, [X0, 0xF]", + "113C0039"), + ("0000C6E4 LDRB W17, [X0, 0xF]", + "113C4039"), + ("0000C6E8 LDRSB X17, [X0, 0xF]", + "113C8039"), + ("0000C6EC LDRSB W17, [X0, 0xF]", + "113CC039"), + ("0000C6F0 STR B17, [X0, 0xF]", + "113C003D"), + ("0000C6F4 LDR B17, [X0, 0xF]", + "113C403D"), + ("0000C6F8 STR Q17, [X0, 0xF0]", + "113C803D"), + ("0000C6FC LDR Q17, [X0, 0xF0]", + "113CC03D"), + ("0000C700 STRH W17, [X0, 0x1E]", + "113C0079"), + ("0000C704 LDRH W17, [X0, 0x1E]", + "113C4079"), + ("0000C708 LDRSH X17, [X0, 0x1E]", + "113C8079"), + ("0000C70C LDRSH W17, [X0, 0x1E]", + "113CC079"), + ("0000C710 STR H17, [X0, 0x1E]", + "113C007D"), + ("0000C714 LDR H17, [X0, 0x1E]", + "113C407D"), + ("0000C720 STR W17, [X0, 0x3C]", + "113C00B9"), + ("0000C724 LDR W17, [X0, 0x3C]", + "113C40B9"), + ("0000C728 LDRSW X17, [X0, 0x3C]", + "113C80B9"), + ("0000C730 STR S17, [X0, 0x3C]", + "113C00BD"), + ("0000C734 LDR S17, [X0, 0x3C]", + "113C40BD"), + ("0000C740 STR X17, [X0, 0x78]", + "113C00F9"), + ("0000C744 LDR X17, [X0, 0x78]", + "113C40F9"), + ("0000C750 STR D17, [X0, 0x78]", + "113C00FD"), + ("0000C754 LDR D17, [X0, 0x78]", + "113C40FD"), + ("0000C760 STURH W7, [X5, 0xF]", + "A7F00078"), + ("0000C764 STRH W7, [X5], 0xF", + "A7F40078"), + ("0000C768 STTRH W7, [X5, 0xF]", + "A7F80078"), + ("0000C76C STRH W7, [X5, 0xF]!", + "A7FC0078"), + ("0000C770 LDURH W7, [X5, 0xF]", + "A7F04078"), + ("0000C774 LDRH W7, [X5], 0xF", + "A7F44078"), + ("0000C778 LDTRH W7, [X5, 0xF]", + "A7F84078"), + ("0000C77C LDRH W7, [X5, 0xF]!", + "A7FC4078"), + ("0000C780 LDURSH X7, [X5, 0xF]", + "A7F08078"), + ("0000C784 LDRSH X7, [X5], 0xF", + "A7F48078"), + ("0000C788 LDTRSH X7, [X5, 0xF]", + "A7F88078"), + ("0000C78C LDRSH X7, [X5, 0xF]!", + "A7FC8078"), + ("0000C790 LDURSH W7, [X5, 0xF]", + "A7F0C078"), + ("0000C794 LDRSH W7, [X5], 0xF", + "A7F4C078"), + ("0000C798 LDTRSH W7, [X5, 0xF]", + "A7F8C078"), + ("0000C79C LDRSH W7, [X5, 0xF]!", + "A7FCC078"), + ("0000C7A0 STUR H7, [X5, 0xF]", + "A7F0007C"), + ("0000C7A4 STR H7, [X5], 0xF", + "A7F4007C"), + ("0000C7A8 STTR H7, [X5, 0xF]", + "A7F8007C"), + ("0000C7AC STR H7, [X5, 0xF]!", + "A7FC007C"), + ("0000C7B0 LDUR H7, [X5, 0xF]", + "A7F0407C"), + ("0000C7B4 LDR H7, [X5], 0xF", + "A7F4407C"), + ("0000C7B8 LDTR H7, [X5, 0xF]", + "A7F8407C"), + ("0000C7BC LDR H7, [X5, 0xF]!", + "A7FC407C"), + ("0000C7E0 STUR W7, [X5, 0xF]", + "A7F000B8"), + ("0000C7E4 STR W7, [X5], 0xF", + "A7F400B8"), + ("0000C7E8 STTR W7, [X5, 0xF]", + "A7F800B8"), + ("0000C7EC STR W7, [X5, 0xF]!", + "A7FC00B8"), + ("0000C7F0 LDUR W7, [X5, 0xF]", + "A7F040B8"), + ("0000C7F4 LDR W7, [X5], 0xF", + "A7F440B8"), + ("0000C7F8 LDTR W7, [X5, 0xF]", + "A7F840B8"), + ("0000C7FC LDR W7, [X5, 0xF]!", + "A7FC40B8"), + ("0000C800 LDURSW X7, [X5, 0xF]", + "A7F080B8"), + ("0000C804 LDRSW X7, [X5], 0xF", + "A7F480B8"), + ("0000C808 LDTRSW X7, [X5, 0xF]", + "A7F880B8"), + ("0000C80C LDRSW X7, [X5, 0xF]!", + "A7FC80B8"), + ("0000C820 STUR S7, [X5, 0xF]", + "A7F000BC"), + ("0000C824 STR S7, [X5], 0xF", + "A7F400BC"), + ("0000C828 STTR S7, [X5, 0xF]", + "A7F800BC"), + ("0000C82C STR S7, [X5, 0xF]!", + "A7FC00BC"), + ("0000C830 LDUR S7, [X5, 0xF]", + "A7F040BC"), + ("0000C834 LDR S7, [X5], 0xF", + "A7F440BC"), + ("0000C838 LDTR S7, [X5, 0xF]", + "A7F840BC"), + ("0000C83C LDR S7, [X5, 0xF]!", + "A7FC40BC"), + ("0000C860 STUR X7, [X5, 0xF]", + "A7F000F8"), + ("0000C864 STR X7, [X5], 0xF", + "A7F400F8"), + ("0000C868 STTR X7, [X5, 0xF]", + "A7F800F8"), + ("0000C86C STR X7, [X5, 0xF]!", + "A7FC00F8"), + ("0000C870 LDUR X7, [X5, 0xF]", + "A7F040F8"), + ("0000C874 LDR X7, [X5], 0xF", + "A7F440F8"), + ("0000C878 LDTR X7, [X5, 0xF]", + "A7F840F8"), + ("0000C87C LDR X7, [X5, 0xF]!", + "A7FC40F8"), + ("0000C8A0 STUR D7, [X5, 0xF]", + "A7F000FC"), + ("0000C8A4 STR D7, [X5], 0xF", + "A7F400FC"), + ("0000C8A8 STTR D7, [X5, 0xF]", + "A7F800FC"), + ("0000C8AC STR D7, [X5, 0xF]!", + "A7FC00FC"), + ("0000C8B0 LDUR D7, [X5, 0xF]", + "A7F040FC"), + ("0000C8B4 LDR D7, [X5], 0xF", + "A7F440FC"), + ("0000C8B8 LDTR D7, [X5, 0xF]", + "A7F840FC"), + ("0000C8BC LDR D7, [X5, 0xF]!", + "A7FC40FC"), + ("0000C8E0 STRB W7, [X7]", + "E7000039"), + ("0000C8E4 LDRB W7, [X7]", + "E7004039"), + ("0000C8E8 LDRSB X7, [X7]", + "E7008039"), + ("0000C8EC LDRSB W7, [X7]", + "E700C039"), + ("0000C8F0 STR B7, [X7]", + "E700003D"), + ("0000C8F4 LDR B7, [X7]", + "E700403D"), + ("0000C8F8 STR Q7, [X7]", + "E700803D"), + ("0000C8FC LDR Q7, [X7]", + "E700C03D"), + ("0000C900 STRH W7, [X7]", + "E7000079"), + ("0000C904 LDRH W7, [X7]", + "E7004079"), + ("0000C908 LDRSH X7, [X7]", + "E7008079"), + ("0000C90C LDRSH W7, [X7]", + "E700C079"), + ("0000C910 STR H7, [X7]", + "E700007D"), + ("0000C914 LDR H7, [X7]", + "E700407D"), + ("0000C920 STR W7, [X7]", + "E70000B9"), + ("0000C924 LDR W7, [X7]", + "E70040B9"), + ("0000C928 LDRSW X7, [X7]", + "E70080B9"), + ("0000C930 STR S7, [X7]", + "E70000BD"), + ("0000C934 LDR S7, [X7]", + "E70040BD"), + ("0000C940 STR X7, [X7]", + "E70000F9"), + ("0000C944 LDR X7, [X7]", + "E70040F9"), + ("0000C950 STR D7, [X7]", + "E70000FD"), + ("0000C954 LDR D7, [X7]", + "E70040FD"), + + + ("0000C6F0 STRB W17, [X3, W7 UXTW 0x0]", + "71482738"), + ("0000C6F8 STRB W17, [X3, X7]", + "71682738"), + ("0000C710 STRB W17, [X3, W7 SXTW 0x0]", + "71C82738"), + ("0000C718 STRB W17, [X3, X7 SXTX 0x0]", + "71E82738"), + ("0000C730 LDRB W17, [X3, W7 UXTW 0x0]", + "71486738"), + ("0000C738 LDRB W17, [X3, X7]", + "71686738"), + ("0000C750 LDRB W17, [X3, W7 SXTW 0x0]", + "71C86738"), + ("0000C758 LDRB W17, [X3, X7 SXTX 0x0]", + "71E86738"), + ("0000C770 LDRSB X17, [X3, W7 UXTW 0x0]", + "7148A738"), + ("0000C778 LDRSB X17, [X3, X7]", + "7168A738"), + ("0000C790 LDRSB X17, [X3, W7 SXTW 0x0]", + "71C8A738"), + ("0000C798 LDRSB X17, [X3, X7 SXTX 0x0]", + "71E8A738"), + ("0000C7B0 LDRSB W17, [X3, W7 UXTW 0x0]", + "7148E738"), + ("0000C7B8 LDRSB W17, [X3, X7]", + "7168E738"), + ("0000C7D0 LDRSB W17, [X3, W7 SXTW 0x0]", + "71C8E738"), + ("0000C7D8 LDRSB W17, [X3, X7 SXTX 0x0]", + "71E8E738"), + ("0000C7F0 STR B17, [X3, W7 UXTW 0x0]", + "7148273C"), + ("0000C7F8 STR B17, [X3, X7]", + "7168273C"), + ("0000C810 STR B17, [X3, W7 SXTW 0x0]", + "71C8273C"), + ("0000C818 STR B17, [X3, X7 SXTX 0x0]", + "71E8273C"), + ("0000C830 LDR B17, [X3, W7 UXTW 0x0]", + "7148673C"), + ("0000C838 LDR B17, [X3, X7]", + "7168673C"), + ("0000C850 LDR B17, [X3, W7 SXTW 0x0]", + "71C8673C"), + ("0000C858 LDR B17, [X3, X7 SXTX 0x0]", + "71E8673C"), + ("0000C870 STR Q17, [X3, W7 UXTW 0x0]", + "7148A73C"), + ("0000C878 STR Q17, [X3, X7]", + "7168A73C"), + ("0000C87C STR Q17, [X3, X7 LSL 0x4]", + "7178A73C"), + ("0000C890 STR Q17, [X3, W7 SXTW 0x0]", + "71C8A73C"), + ("0000C894 STR Q17, [X3, W7 SXTW 0x4]", + "71D8A73C"), + ("0000C898 STR Q17, [X3, X7 SXTX 0x0]", + "71E8A73C"), + ("0000C89C STR Q17, [X3, X7 SXTX 0x4]", + "71F8A73C"), + ("0000C8B0 LDR Q17, [X3, W7 UXTW 0x0]", + "7148E73C"), + ("0000C8B4 LDR Q17, [X3, W7 UXTW 0x4]", + "7158E73C"), + ("0000C8B8 LDR Q17, [X3, X7]", + "7168E73C"), + ("0000C8BC LDR Q17, [X3, X7 LSL 0x4]", + "7178E73C"), + ("0000C8D0 LDR Q17, [X3, W7 SXTW 0x0]", + "71C8E73C"), + ("0000C8D4 LDR Q17, [X3, W7 SXTW 0x4]", + "71D8E73C"), + ("0000C8D8 LDR Q17, [X3, X7 SXTX 0x0]", + "71E8E73C"), + ("0000C8DC LDR Q17, [X3, X7 SXTX 0x4]", + "71F8E73C"), + ("0000C8F0 STRH W17, [X3, W7 UXTW 0x0]", + "71482778"), + ("0000C8F4 STRH W17, [X3, W7 UXTW 0x1]", + "71582778"), + ("0000C8F8 STRH W17, [X3, X7]", + "71682778"), + ("0000C8FC STRH W17, [X3, X7 LSL 0x1]", + "71782778"), + ("0000C910 STRH W17, [X3, W7 SXTW 0x0]", + "71C82778"), + ("0000C914 STRH W17, [X3, W7 SXTW 0x1]", + "71D82778"), + ("0000C918 STRH W17, [X3, X7 SXTX 0x0]", + "71E82778"), + ("0000C91C STRH W17, [X3, X7 SXTX 0x1]", + "71F82778"), + ("0000C930 LDRH W17, [X3, W7 UXTW 0x0]", + "71486778"), + ("0000C934 LDRH W17, [X3, W7 UXTW 0x1]", + "71586778"), + ("0000C938 LDRH W17, [X3, X7]", + "71686778"), + ("0000C93C LDRH W17, [X3, X7 LSL 0x1]", + "71786778"), + ("0000C950 LDRH W17, [X3, W7 SXTW 0x0]", + "71C86778"), + ("0000C954 LDRH W17, [X3, W7 SXTW 0x1]", + "71D86778"), + ("0000C958 LDRH W17, [X3, X7 SXTX 0x0]", + "71E86778"), + ("0000C95C LDRH W17, [X3, X7 SXTX 0x1]", + "71F86778"), + ("0000C970 LDRSH X17, [X3, W7 UXTW 0x0]", + "7148A778"), + ("0000C974 LDRSH X17, [X3, W7 UXTW 0x1]", + "7158A778"), + ("0000C978 LDRSH X17, [X3, X7]", + "7168A778"), + ("0000C97C LDRSH X17, [X3, X7 LSL 0x1]", + "7178A778"), + ("0000C990 LDRSH X17, [X3, W7 SXTW 0x0]", + "71C8A778"), + ("0000C994 LDRSH X17, [X3, W7 SXTW 0x1]", + "71D8A778"), + ("0000C998 LDRSH X17, [X3, X7 SXTX 0x0]", + "71E8A778"), + ("0000C99C LDRSH X17, [X3, X7 SXTX 0x1]", + "71F8A778"), + ("0000C9B0 LDRSH W17, [X3, W7 UXTW 0x0]", + "7148E778"), + ("0000C9B4 LDRSH W17, [X3, W7 UXTW 0x1]", + "7158E778"), + ("0000C9B8 LDRSH W17, [X3, X7]", + "7168E778"), + ("0000C9BC LDRSH W17, [X3, X7 LSL 0x1]", + "7178E778"), + ("0000C9D0 LDRSH W17, [X3, W7 SXTW 0x0]", + "71C8E778"), + ("0000C9D4 LDRSH W17, [X3, W7 SXTW 0x1]", + "71D8E778"), + ("0000C9D8 LDRSH W17, [X3, X7 SXTX 0x0]", + "71E8E778"), + ("0000C9DC LDRSH W17, [X3, X7 SXTX 0x1]", + "71F8E778"), + ("0000C9F0 STR H17, [X3, W7 UXTW 0x0]", + "7148277C"), + ("0000C9F4 STR H17, [X3, W7 UXTW 0x1]", + "7158277C"), + ("0000C9F8 STR H17, [X3, X7]", + "7168277C"), + ("0000C9FC STR H17, [X3, X7 LSL 0x1]", + "7178277C"), + ("0000CA10 STR H17, [X3, W7 SXTW 0x0]", + "71C8277C"), + ("0000CA14 STR H17, [X3, W7 SXTW 0x1]", + "71D8277C"), + ("0000CA18 STR H17, [X3, X7 SXTX 0x0]", + "71E8277C"), + ("0000CA1C STR H17, [X3, X7 SXTX 0x1]", + "71F8277C"), + ("0000CA30 LDR H17, [X3, W7 UXTW 0x0]", + "7148677C"), + ("0000CA34 LDR H17, [X3, W7 UXTW 0x1]", + "7158677C"), + ("0000CA38 LDR H17, [X3, X7]", + "7168677C"), + ("0000CA3C LDR H17, [X3, X7 LSL 0x1]", + "7178677C"), + ("0000CA50 LDR H17, [X3, W7 SXTW 0x0]", + "71C8677C"), + ("0000CA54 LDR H17, [X3, W7 SXTW 0x1]", + "71D8677C"), + ("0000CA58 LDR H17, [X3, X7 SXTX 0x0]", + "71E8677C"), + ("0000CA5C LDR H17, [X3, X7 SXTX 0x1]", + "71F8677C"), + ("0000CAF0 STR W17, [X3, W7 UXTW 0x0]", + "714827B8"), + ("0000CAF4 STR W17, [X3, W7 UXTW 0x2]", + "715827B8"), + ("0000CAF8 STR W17, [X3, X7]", + "716827B8"), + ("0000CAFC STR W17, [X3, X7 LSL 0x2]", + "717827B8"), + ("0000CB10 STR W17, [X3, W7 SXTW 0x0]", + "71C827B8"), + ("0000CB14 STR W17, [X3, W7 SXTW 0x2]", + "71D827B8"), + ("0000CB18 STR W17, [X3, X7 SXTX 0x0]", + "71E827B8"), + ("0000CB1C STR W17, [X3, X7 SXTX 0x2]", + "71F827B8"), + ("0000CB30 LDR W17, [X3, W7 UXTW 0x0]", + "714867B8"), + ("0000CB34 LDR W17, [X3, W7 UXTW 0x2]", + "715867B8"), + ("0000CB38 LDR W17, [X3, X7]", + "716867B8"), + ("0000CB3C LDR W17, [X3, X7 LSL 0x2]", + "717867B8"), + ("0000CB50 LDR W17, [X3, W7 SXTW 0x0]", + "71C867B8"), + ("0000CB54 LDR W17, [X3, W7 SXTW 0x2]", + "71D867B8"), + ("0000CB58 LDR W17, [X3, X7 SXTX 0x0]", + "71E867B8"), + ("0000CB5C LDR W17, [X3, X7 SXTX 0x2]", + "71F867B8"), + ("0000CB70 LDRSW X17, [X3, W7 UXTW 0x0]", + "7148A7B8"), + ("0000CB74 LDRSW X17, [X3, W7 UXTW 0x2]", + "7158A7B8"), + ("0000CB78 LDRSW X17, [X3, X7]", + "7168A7B8"), + ("0000CB7C LDRSW X17, [X3, X7 LSL 0x2]", + "7178A7B8"), + ("0000CB90 LDRSW X17, [X3, W7 SXTW 0x0]", + "71C8A7B8"), + ("0000CB94 LDRSW X17, [X3, W7 SXTW 0x2]", + "71D8A7B8"), + ("0000CB98 LDRSW X17, [X3, X7 SXTX 0x0]", + "71E8A7B8"), + ("0000CB9C LDRSW X17, [X3, X7 SXTX 0x2]", + "71F8A7B8"), + ("0000CBF0 STR S17, [X3, W7 UXTW 0x0]", + "714827BC"), + ("0000CBF4 STR S17, [X3, W7 UXTW 0x2]", + "715827BC"), + ("0000CBF8 STR S17, [X3, X7]", + "716827BC"), + ("0000CBFC STR S17, [X3, X7 LSL 0x2]", + "717827BC"), + ("0000CC10 STR S17, [X3, W7 SXTW 0x0]", + "71C827BC"), + ("0000CC14 STR S17, [X3, W7 SXTW 0x2]", + "71D827BC"), + ("0000CC18 STR S17, [X3, X7 SXTX 0x0]", + "71E827BC"), + ("0000CC1C STR S17, [X3, X7 SXTX 0x2]", + "71F827BC"), + ("0000CC30 LDR S17, [X3, W7 UXTW 0x0]", + "714867BC"), + ("0000CC34 LDR S17, [X3, W7 UXTW 0x2]", + "715867BC"), + ("0000CC38 LDR S17, [X3, X7]", + "716867BC"), + ("0000CC3C LDR S17, [X3, X7 LSL 0x2]", + "717867BC"), + ("0000CC50 LDR S17, [X3, W7 SXTW 0x0]", + "71C867BC"), + ("0000CC54 LDR S17, [X3, W7 SXTW 0x2]", + "71D867BC"), + ("0000CC58 LDR S17, [X3, X7 SXTX 0x0]", + "71E867BC"), + ("0000CC5C LDR S17, [X3, X7 SXTX 0x2]", + "71F867BC"), + ("0000CCF0 STR X17, [X3, W7 UXTW 0x0]", + "714827F8"), + ("0000CCF4 STR X17, [X3, W7 UXTW 0x3]", + "715827F8"), + ("0000CCF8 STR X17, [X3, X7]", + "716827F8"), + ("0000CCFC STR X17, [X3, X7 LSL 0x3]", + "717827F8"), + ("0000CD10 STR X17, [X3, W7 SXTW 0x0]", + "71C827F8"), + ("0000CD14 STR X17, [X3, W7 SXTW 0x3]", + "71D827F8"), + ("0000CD18 STR X17, [X3, X7 SXTX 0x0]", + "71E827F8"), + ("0000CD1C STR X17, [X3, X7 SXTX 0x3]", + "71F827F8"), + ("0000CD30 LDR X17, [X3, W7 UXTW 0x0]", + "714867F8"), + ("0000CD34 LDR X17, [X3, W7 UXTW 0x3]", + "715867F8"), + ("0000CD38 LDR X17, [X3, X7]", + "716867F8"), + ("0000CD3C LDR X17, [X3, X7 LSL 0x3]", + "717867F8"), + ("0000CD50 LDR X17, [X3, W7 SXTW 0x0]", + "71C867F8"), + ("0000CD54 LDR X17, [X3, W7 SXTW 0x3]", + "71D867F8"), + ("0000CD58 LDR X17, [X3, X7 SXTX 0x0]", + "71E867F8"), + ("0000CD5C LDR X17, [X3, X7 SXTX 0x3]", + "71F867F8"), + ("0000CDF0 STR D17, [X3, W7 UXTW 0x0]", + "714827FC"), + ("0000CDF4 STR D17, [X3, W7 UXTW 0x3]", + "715827FC"), + ("0000CDF8 STR D17, [X3, X7]", + "716827FC"), + ("0000CDFC STR D17, [X3, X7 LSL 0x3]", + "717827FC"), + ("0000CE10 STR D17, [X3, W7 SXTW 0x0]", + "71C827FC"), + ("0000CE14 STR D17, [X3, W7 SXTW 0x3]", + "71D827FC"), + ("0000CE18 STR D17, [X3, X7 SXTX 0x0]", + "71E827FC"), + ("0000CE1C STR D17, [X3, X7 SXTX 0x3]", + "71F827FC"), + ("0000CE30 LDR D17, [X3, W7 UXTW 0x0]", + "714867FC"), + ("0000CE34 LDR D17, [X3, W7 UXTW 0x3]", + "715867FC"), + ("0000CE38 LDR D17, [X3, X7]", + "716867FC"), + ("0000CE3C LDR D17, [X3, X7 LSL 0x3]", + "717867FC"), + ("0000CE50 LDR D17, [X3, W7 SXTW 0x0]", + "71C867FC"), + ("0000CE54 LDR D17, [X3, W7 SXTW 0x3]", + "71D867FC"), + ("0000CE58 LDR D17, [X3, X7 SXTX 0x0]", + "71E867FC"), + ("0000CE5C LDR D17, [X3, X7 SXTX 0x3]", + "71F867FC"), + + + + ("0000C6F8 STP D10, D11, [SP, 0x68]", + "EAAF066D"), + ("004009E4 STP X29, LR, [SP, 0xFFFFFFFFFFFFFFF0]!", + "FD7BBFA9"), + + ("0000C6E0 STP W3, W15, [X3], 0x7C", + "63BC8F28"), + ("0000C6E4 LDP W3, W15, [X3], 0x7C", + "63BCCF28"), + ("0000C6E8 STP W3, W15, [X3, 0x7C]!", + "63BC8F29"), + ("0000C6EC LDP W3, W15, [X3, 0x7C]!", + "63BCCF29"), + ("0000C6F0 STP X3, X15, [X3], 0xF8", + "63BC8FA8"), + ("0000C6F4 LDP X3, X15, [X3], 0xF8", + "63BCCFA8"), + ("0000C6F8 STP X3, X15, [X3, 0xF8]!", + "63BC8FA9"), + ("0000C6FC LDP X3, X15, [X3, 0xF8]!", + "63BCCFA9"), + + ("0000C6E0 STP S3, S15, [X3], 0x7C", + "63BC8F2C"), + ("0000C6E4 LDP S3, S15, [X3], 0x7C", + "63BCCF2C"), + ("0000C6E8 STP S3, S15, [X3, 0x7C]!", + "63BC8F2D"), + ("0000C6EC LDP S3, S15, [X3, 0x7C]!", + "63BCCF2D"), + ("0000C6F0 STP D3, D15, [X3], 0xF8", + "63BC8F6C"), + ("0000C6F4 LDP D3, D15, [X3], 0xF8", + "63BCCF6C"), + ("0000C6F8 STP D3, D15, [X3, 0xF8]!", + "63BC8F6D"), + ("0000C6FC LDP D3, D15, [X3, 0xF8]!", + "63BCCF6D"), + ("0000C700 STP Q3, Q15, [X3], 0x1F0", + "63BC8FAC"), + ("0000C704 LDP Q3, Q15, [X3], 0x1F0", + "63BCCFAC"), + ("0000C708 STP Q3, Q15, [X3, 0x1F0]!", + "63BC8FAD"), + ("0000C70C LDP Q3, Q15, [X3, 0x1F0]!", + "63BCCFAD"), + + ("00028614 STP D8, D9, [SP, 0x70]", + "E827076D"), + + + + ("0000C6E0 RBIT W3, W3", + "6300C05A"), + ("0000C6E4 REV16 W3, W3", + "6304C05A"), + ("0000C6E8 REV W3, W3", + "6308C05A"), + ("0000C6F0 CLZ W3, W3", + "6310C05A"), + ("0000C6F4 CLS W3, W3", + "6314C05A"), + ("0000C710 RBIT X3, X3", + "6300C0DA"), + ("0000C714 REV16 X3, X3", + "6304C0DA"), + ("0000C718 REV32 X3, X3", + "6308C0DA"), + ("0000C71C REV X3, X3", + "630CC0DA"), + ("0000C720 CLZ X3, X3", + "6310C0DA"), + ("0000C724 CLS X3, X3", + "6314C0DA"), + + ("00028678 CBNZ W0, 0x24", + "20010035"), + ("0000C734 CBZ X1, 0x4C4", + "212600B4"), + + ("0000D088 FMOV D10, D0", + "0A40601E"), + ("0000C710 FMOV D14, X0", + "0E00679E"), + ("0000C738 FMOV X0, D14", + "C001669E"), + ("00010308 FMOV W0, S12", + "8001261E"), + + ("0000CC94 FSUB D0, D5, D0", + "A038601E"), + ("0000D1A4 FADD D0, D1, D10", + "20286A1E"), + ("00044DB4 FDIV D1, D0, D8", + "0118681E"), + ("0001AB48 FMUL D0, D8, D0", + "0009601E"), + ("0001C5C0 FMUL S0, S0, S1", + "0008211E"), + ("0000CCA0 FMADD D1, D0, D4, D1", + "0104441F"), + ("0002F938 FMSUB D2, D2, D1, D3", + "428C411F"), + ("0000CFE8 FABS D10, D8", + "0AC1601E"), + ("00010014 FNEG D11, D0", + "0B40611E"), + ("0000CCBC FMOV D0, 0x40", + "0010681E"), + ("0008BD54 FCMP D0, D1", + "0020611E"), + ("0000C6E4 FCMP S3, 0x0", + "6820201E"), + ("0000C6EC FCMP D3, 0x0", + "6820601E"), + ("0008BD54 FCMP D0, D1", + "0020611E"), + ("0000F58C FCMPE D8, 0x0", + "1821601E"), + + + ("0000CD28 FCVTZU W1, D0", + "0100791E"), + ("0000CAB0 FCVTZS X2, D0", + "0200789E"), + ("0001C5C4 FCVT D0, S0", + "00C0221E"), + ("0002F90C FCVT S1, D0", + "0140621E"), + + + ("0000CCA4 SCVTF D0, W5", + "A000621E"), + ("0000CAC0 SCVTF D1, X2", + "4100629E"), + ("0000CD6C UCVTF D1, W0", + "0100631E"), + + ("0003D25C UBFM X1, X0, 0x3D, 0x3", + "010C7DD3"), + + ("0000C6E0 CSEL W7, W3, W1, EQ", + "6700811A"), + ("0000C6E4 CSINC W7, W3, W1, EQ", + "6704811A"), + ("0000C6E8 CSINV W7, W3, W1, EQ", + "6700815A"), + ("0000C6EC CSNEG W7, W3, W1, EQ", + "6704815A"), + ("0000C6F0 CSEL W7, W3, W1, CC", + "6730811A"), + ("0000C6F4 CSINC W7, W3, W1, CC", + "6734811A"), + ("0000C6F8 CSINV W7, W3, W1, CC", + "6730815A"), + ("0000C6FC CSNEG W7, W3, W1, CC", + "6734815A"), + ("0000C700 CSEL W7, W3, W1, NV", + "67F0811A"), + ("0000C704 CSINC W7, W3, W1, NV", + "67F4811A"), + ("0000C708 CSINV W7, W3, W1, NV", + "67F0815A"), + ("0000C70C CSNEG W7, W3, W1, NV", + "67F4815A"), + ("0000C710 CSEL W7, W3, W1, EQ", + "6700811A"), + ("0000C714 CSINC W7, W3, W1, EQ", + "6704811A"), + ("0000C718 CSINV W7, W3, W1, EQ", + "6700815A"), + ("0000C71C CSNEG W7, W3, W1, EQ", + "6704815A"), + ("0000C720 CSEL W7, W3, W1, CC", + "6730811A"), + ("0000C724 CSINC W7, W3, W1, CC", + "6734811A"), + ("0000C728 CSINV W7, W3, W1, CC", + "6730815A"), + ("0000C72C CSNEG W7, W3, W1, CC", + "6734815A"), + ("0000C730 CSEL W7, W3, W1, NV", + "67F0811A"), + ("0000C734 CSINC W7, W3, W1, NV", + "67F4811A"), + ("0000C738 CSINV W7, W3, W1, NV", + "67F0815A"), + ("0000C73C CSNEG W7, W3, W1, NV", + "67F4815A"), + ("0000C740 CSEL X7, X3, X1, EQ", + "6700819A"), + ("0000C744 CSINC X7, X3, X1, EQ", + "6704819A"), + ("0000C748 CSINV X7, X3, X1, EQ", + "670081DA"), + ("0000C74C CSNEG X7, X3, X1, EQ", + "670481DA"), + ("0000C750 CSEL X7, X3, X1, CC", + "6730819A"), + ("0000C754 CSINC X7, X3, X1, CC", + "6734819A"), + ("0000C758 CSINV X7, X3, X1, CC", + "673081DA"), + ("0000C75C CSNEG X7, X3, X1, CC", + "673481DA"), + ("0000C760 CSEL X7, X3, X1, NV", + "67F0819A"), + ("0000C764 CSINC X7, X3, X1, NV", + "67F4819A"), + ("0000C768 CSINV X7, X3, X1, NV", + "67F081DA"), + ("0000C76C CSNEG X7, X3, X1, NV", + "67F481DA"), + ("0000C770 CSEL X7, X3, X1, EQ", + "6700819A"), + ("0000C774 CSINC X7, X3, X1, EQ", + "6704819A"), + ("0000C778 CSINV X7, X3, X1, EQ", + "670081DA"), + ("0000C77C CSNEG X7, X3, X1, EQ", + "670481DA"), + ("0000C780 CSEL X7, X3, X1, CC", + "6730819A"), + ("0000C784 CSINC X7, X3, X1, CC", + "6734819A"), + ("0000C788 CSINV X7, X3, X1, CC", + "673081DA"), + ("0000C78C CSNEG X7, X3, X1, CC", + "673481DA"), + ("0000C790 CSEL X7, X3, X1, NV", + "67F0819A"), + ("0000C794 CSINC X7, X3, X1, NV", + "67F4819A"), + ("0000C798 CSINV X7, X3, X1, NV", + "67F081DA"), + ("0000C79C CSNEG X7, X3, X1, NV", + "67F481DA"), + ("0000DEB8 CSET W0, NE", + "E0079F1A"), + ("00031190 CSET X3, NE", + "E3079F9A"), + ("00068EE4 CSETM W19, NE", + "F3039F5A"), + ("00083E20 CSETM W19, MI", + "F3539F5A"), + ("0000D7FC CSINC W2, W2, W2, NE", + "4214821A"), + ("0007FB50 CSNEG W0, W0, W0, EQ", + "0004805A"), + + + + + ("000A3304 TBNZ W19, 0x1F, 0xFFFFFFFFFFFFFEEC", + "73F7FF37"), + ("0000CA34 TBZ W0, 0x1F, 0x1C", + "E000F836"), + ("0001332C TBZ X19, 0x3F, 0x14", + "B300F8B6"), + + ("0006BC4C MADD X15, X15, X0, XZR", + "EF7D009B"), + ("0000EAC0 MADD W22, W0, W22, W1", + "1604161B"), + ("00011F00 MSUB W0, W4, W3, W0", + "8080031B"), + ("0001A1B8 MSUB X0, X0, X1, X22", + "00D8019B"), + ("000100C8 SMADDL X25, W25, W20, X0", + "3903349B"), + ("00055860 UMADDL X0, W0, W20, X1", + "0004B49B"), + ("00462068 UMULH X10, X5, X9", + "AA7CC99B"), + + ("0003A290 UDIV W1, W23, W1", + "E10AC11A"), + ("0000D26C SDIV X1, X0, X1", + "010CC19A"), + + ("0000CC50 LDR D4, 0xD0", + "8406005C"), + + ("0000CC90 LSL W5, W7, W3", + "E520C31A"), + ("0000D5B0 LSL X1, X1, X6", + "2120C69A"), + ("0001CE98 ASR W0, W0, W20", + "0028D41A"), + ("0005DD30 ASR X19, X3, X19", + "7328D39A"), + ("0001B118 LSR W4, W1, W3", + "2424C31A"), + ("000374E8 LSR X3, X4, X1", + "8324C19A"), + ("0009EB84 ROR X3, X3, X6", + "632CC69A"), + ("00050634 NOP ", + "1F2003D5"), + + ("0006C588 EXTR W2, W2, W2, 0x1F", + "427C8213"), + + ("00458AB8 CCMP X3, X5, 0x8, GE", + "68A045FA"), + ("00458F90 CCMP W3, 0x1, 0x0, CS", + "6028417A"), + + ("00463288 SVC 0x0", + "010000D4"), + + + ("00458FF4 MRS X0, 0x3, c13, c0, 0x2", + "40D03BD5"), + ("0045BA04 MSR 0x3, c13, c0, 0x2, X0", + "40D01BD5"), + ("0048A2E8 MRS X13, 0x3, c4, c4, 0x0", + "0D443BD5"), + ("0048A9DC MRS X0, 0x3, c4, c4, 0x1", + "20443BD5"), + + ("004010C8 ORR W2, 0x0, 0x1", + "E2030032"), + + ("0045B008 LDXR W7, [X19]", + "677E5F88"), + ("0045AEC4 LDXR W13, [X19]", + "6D7E5F88"), + ("0045B014 STXR W2, W6, [X19]", + "667E0288"), + + ("00464084 LDAXR W13, [X20]", + "8DFE5F88"), + ("0046FA7C LDAXR X17, [X16]", + "11FE5FC8"), + ("00464090 STLXR W14, W2, [X20]", + "82FE0E88"), + + ("0045ADB0 DMB c11", + "BF3B03D5"), + + ("00484A08 BRK 0x3E8", + "007D20D4"), +] + + + +def h2i(s): + return s.replace(' ', '').decode('hex') + + +ts = time.time() + +for s, l in reg_tests_aarch64[:]: + print "-" * 80 + print s[:12], l + s = s[12:] + b = h2i((l)) + mn = mn_aarch64.dis(b, 'l') + print [str(x) for x in mn.args] + print s + print mn + assert(str(mn) == s) + l = mn_aarch64.fromstring(s, 'l') + assert(str(l) == s) + a = mn_aarch64.asm(l) + print [x for x in a] + print repr(b) + assert(b in a) + diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 93b651c0..2109aa53 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -63,6 +63,525 @@ m64 = 64 # (64, 64) reg_tests = [ + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EAX]", + "0fea00"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [ECX]", + "0fea01"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EDX]", + "0fea02"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EBX]", + "0fea03"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EAX+EDX*0x4]", + "0fea0490"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [0x90909090]", + "0fea0590909090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [ESI]", + "0fea06"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EDI]", + "0fea07"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EAX]", + "0fea08"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [ECX]", + "0fea09"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EDX]", + "0fea0a"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EBX]", + "0fea0b"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EAX+EDX*0x4]", + "0fea0c90"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [0x90909090]", + "0fea0d90909090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [ESI]", + "0fea0e"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EDI]", + "0fea0f"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EAX]", + "0fea10"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [ECX]", + "0fea11"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EDX]", + "0fea12"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EBX]", + "0fea13"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EAX+EDX*0x4]", + "0fea1490"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [0x90909090]", + "0fea1590909090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [ESI]", + "0fea16"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EDI]", + "0fea17"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EAX]", + "0fea18"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [ECX]", + "0fea19"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EDX]", + "0fea1a"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EBX]", + "0fea1b"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EAX+EDX*0x4]", + "0fea1c90"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [0x90909090]", + "0fea1d90909090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [ESI]", + "0fea1e"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EDI]", + "0fea1f"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EAX]", + "0fea20"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [ECX]", + "0fea21"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EDX]", + "0fea22"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EBX]", + "0fea23"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EAX+EDX*0x4]", + "0fea2490"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [0x90909090]", + "0fea2590909090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [ESI]", + "0fea26"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EDI]", + "0fea27"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EAX]", + "0fea28"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [ECX]", + "0fea29"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EDX]", + "0fea2a"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EBX]", + "0fea2b"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EAX+EDX*0x4]", + "0fea2c90"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [0x90909090]", + "0fea2d90909090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [ESI]", + "0fea2e"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EDI]", + "0fea2f"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EAX]", + "0fea30"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [ECX]", + "0fea31"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EDX]", + "0fea32"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EBX]", + "0fea33"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EAX+EDX*0x4]", + "0fea3490"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [0x90909090]", + "0fea3590909090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [ESI]", + "0fea36"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EDI]", + "0fea37"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EAX]", + "0fea38"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [ECX]", + "0fea39"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EDX]", + "0fea3a"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EBX]", + "0fea3b"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EAX+EDX*0x4]", + "0fea3c90"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [0x90909090]", + "0fea3d90909090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [ESI]", + "0fea3e"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EDI]", + "0fea3f"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EAX+0xFFFFFF90]", + "0fea4090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [ECX+0xFFFFFF90]", + "0fea4190"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EDX+0xFFFFFF90]", + "0fea4290"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EBX+0xFFFFFF90]", + "0fea4390"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EAX+EDX*0x4+0xFFFFFF90]", + "0fea449090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EBP+0xFFFFFF90]", + "0fea4590"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [ESI+0xFFFFFF90]", + "0fea4690"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EDI+0xFFFFFF90]", + "0fea4790"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EAX+0xFFFFFF90]", + "0fea4890"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [ECX+0xFFFFFF90]", + "0fea4990"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EDX+0xFFFFFF90]", + "0fea4a90"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EBX+0xFFFFFF90]", + "0fea4b90"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EAX+EDX*0x4+0xFFFFFF90]", + "0fea4c9090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EBP+0xFFFFFF90]", + "0fea4d90"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [ESI+0xFFFFFF90]", + "0fea4e90"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EDI+0xFFFFFF90]", + "0fea4f90"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EAX+0xFFFFFF90]", + "0fea5090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [ECX+0xFFFFFF90]", + "0fea5190"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EDX+0xFFFFFF90]", + "0fea5290"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EBX+0xFFFFFF90]", + "0fea5390"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EAX+EDX*0x4+0xFFFFFF90]", + "0fea549090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EBP+0xFFFFFF90]", + "0fea5590"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [ESI+0xFFFFFF90]", + "0fea5690"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EDI+0xFFFFFF90]", + "0fea5790"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EAX+0xFFFFFF90]", + "0fea5890"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [ECX+0xFFFFFF90]", + "0fea5990"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EDX+0xFFFFFF90]", + "0fea5a90"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EBX+0xFFFFFF90]", + "0fea5b90"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EAX+EDX*0x4+0xFFFFFF90]", + "0fea5c9090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EBP+0xFFFFFF90]", + "0fea5d90"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [ESI+0xFFFFFF90]", + "0fea5e90"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EDI+0xFFFFFF90]", + "0fea5f90"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EAX+0xFFFFFF90]", + "0fea6090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [ECX+0xFFFFFF90]", + "0fea6190"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EDX+0xFFFFFF90]", + "0fea6290"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EBX+0xFFFFFF90]", + "0fea6390"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EAX+EDX*0x4+0xFFFFFF90]", + "0fea649090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EBP+0xFFFFFF90]", + "0fea6590"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [ESI+0xFFFFFF90]", + "0fea6690"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EDI+0xFFFFFF90]", + "0fea6790"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EAX+0xFFFFFF90]", + "0fea6890"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [ECX+0xFFFFFF90]", + "0fea6990"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EDX+0xFFFFFF90]", + "0fea6a90"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EBX+0xFFFFFF90]", + "0fea6b90"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EAX+EDX*0x4+0xFFFFFF90]", + "0fea6c9090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EBP+0xFFFFFF90]", + "0fea6d90"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [ESI+0xFFFFFF90]", + "0fea6e90"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EDI+0xFFFFFF90]", + "0fea6f90"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EAX+0xFFFFFF90]", + "0fea7090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [ECX+0xFFFFFF90]", + "0fea7190"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EDX+0xFFFFFF90]", + "0fea7290"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EBX+0xFFFFFF90]", + "0fea7390"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EAX+EDX*0x4+0xFFFFFF90]", + "0fea749090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EBP+0xFFFFFF90]", + "0fea7590"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [ESI+0xFFFFFF90]", + "0fea7690"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EDI+0xFFFFFF90]", + "0fea7790"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EAX+0xFFFFFF90]", + "0fea7890"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [ECX+0xFFFFFF90]", + "0fea7990"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EDX+0xFFFFFF90]", + "0fea7a90"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EBX+0xFFFFFF90]", + "0fea7b90"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EAX+EDX*0x4+0xFFFFFF90]", + "0fea7c9090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EBP+0xFFFFFF90]", + "0fea7d90"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [ESI+0xFFFFFF90]", + "0fea7e90"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EDI+0xFFFFFF90]", + "0fea7f90"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EAX+0x90909090]", + "0fea8090909090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [ECX+0x90909090]", + "0fea8190909090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EDX+0x90909090]", + "0fea8290909090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EBX+0x90909090]", + "0fea8390909090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EAX+EDX*0x4+0x90909090]", + "0fea849090909090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EBP+0x90909090]", + "0fea8590909090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [ESI+0x90909090]", + "0fea8690909090"), + (m32, "XXXXXXXX PMINSW MM0, QWORD PTR [EDI+0x90909090]", + "0fea8790909090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EAX+0x90909090]", + "0fea8890909090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [ECX+0x90909090]", + "0fea8990909090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EDX+0x90909090]", + "0fea8a90909090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EBX+0x90909090]", + "0fea8b90909090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EAX+EDX*0x4+0x90909090]", + "0fea8c9090909090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EBP+0x90909090]", + "0fea8d90909090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [ESI+0x90909090]", + "0fea8e90909090"), + (m32, "XXXXXXXX PMINSW MM1, QWORD PTR [EDI+0x90909090]", + "0fea8f90909090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EAX+0x90909090]", + "0fea9090909090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [ECX+0x90909090]", + "0fea9190909090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EDX+0x90909090]", + "0fea9290909090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EBX+0x90909090]", + "0fea9390909090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EAX+EDX*0x4+0x90909090]", + "0fea949090909090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EBP+0x90909090]", + "0fea9590909090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [ESI+0x90909090]", + "0fea9690909090"), + (m32, "XXXXXXXX PMINSW MM2, QWORD PTR [EDI+0x90909090]", + "0fea9790909090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EAX+0x90909090]", + "0fea9890909090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [ECX+0x90909090]", + "0fea9990909090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EDX+0x90909090]", + "0fea9a90909090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EBX+0x90909090]", + "0fea9b90909090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EAX+EDX*0x4+0x90909090]", + "0fea9c9090909090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EBP+0x90909090]", + "0fea9d90909090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [ESI+0x90909090]", + "0fea9e90909090"), + (m32, "XXXXXXXX PMINSW MM3, QWORD PTR [EDI+0x90909090]", + "0fea9f90909090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EAX+0x90909090]", + "0feaa090909090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [ECX+0x90909090]", + "0feaa190909090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EDX+0x90909090]", + "0feaa290909090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EBX+0x90909090]", + "0feaa390909090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EAX+EDX*0x4+0x90909090]", + "0feaa49090909090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EBP+0x90909090]", + "0feaa590909090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [ESI+0x90909090]", + "0feaa690909090"), + (m32, "XXXXXXXX PMINSW MM4, QWORD PTR [EDI+0x90909090]", + "0feaa790909090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EAX+0x90909090]", + "0feaa890909090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [ECX+0x90909090]", + "0feaa990909090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EDX+0x90909090]", + "0feaaa90909090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EBX+0x90909090]", + "0feaab90909090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EAX+EDX*0x4+0x90909090]", + "0feaac9090909090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EBP+0x90909090]", + "0feaad90909090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [ESI+0x90909090]", + "0feaae90909090"), + (m32, "XXXXXXXX PMINSW MM5, QWORD PTR [EDI+0x90909090]", + "0feaaf90909090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EAX+0x90909090]", + "0feab090909090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [ECX+0x90909090]", + "0feab190909090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EDX+0x90909090]", + "0feab290909090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EBX+0x90909090]", + "0feab390909090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EAX+EDX*0x4+0x90909090]", + "0feab49090909090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EBP+0x90909090]", + "0feab590909090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [ESI+0x90909090]", + "0feab690909090"), + (m32, "XXXXXXXX PMINSW MM6, QWORD PTR [EDI+0x90909090]", + "0feab790909090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EAX+0x90909090]", + "0feab890909090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [ECX+0x90909090]", + "0feab990909090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EDX+0x90909090]", + "0feaba90909090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EBX+0x90909090]", + "0feabb90909090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EAX+EDX*0x4+0x90909090]", + "0feabc9090909090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EBP+0x90909090]", + "0feabd90909090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [ESI+0x90909090]", + "0feabe90909090"), + (m32, "XXXXXXXX PMINSW MM7, QWORD PTR [EDI+0x90909090]", + "0feabf90909090"), + (m32, "XXXXXXXX PMINSW MM0, MM0", + "0feac0"), + (m32, "XXXXXXXX PMINSW MM0, MM1", + "0feac1"), + (m32, "XXXXXXXX PMINSW MM0, MM2", + "0feac2"), + (m32, "XXXXXXXX PMINSW MM0, MM3", + "0feac3"), + (m32, "XXXXXXXX PMINSW MM0, MM4", + "0feac4"), + (m32, "XXXXXXXX PMINSW MM0, MM5", + "0feac5"), + (m32, "XXXXXXXX PMINSW MM0, MM6", + "0feac6"), + (m32, "XXXXXXXX PMINSW MM0, MM7", + "0feac7"), + (m32, "XXXXXXXX PMINSW MM1, MM0", + "0feac8"), + (m32, "XXXXXXXX PMINSW MM1, MM1", + "0feac9"), + (m32, "XXXXXXXX PMINSW MM1, MM2", + "0feaca"), + (m32, "XXXXXXXX PMINSW MM1, MM3", + "0feacb"), + (m32, "XXXXXXXX PMINSW MM1, MM4", + "0feacc"), + (m32, "XXXXXXXX PMINSW MM1, MM5", + "0feacd"), + (m32, "XXXXXXXX PMINSW MM1, MM6", + "0feace"), + (m32, "XXXXXXXX PMINSW MM1, MM7", + "0feacf"), + (m32, "XXXXXXXX PMINSW MM2, MM0", + "0fead0"), + (m32, "XXXXXXXX PMINSW MM2, MM1", + "0fead1"), + (m32, "XXXXXXXX PMINSW MM2, MM2", + "0fead2"), + (m32, "XXXXXXXX PMINSW MM2, MM3", + "0fead3"), + (m32, "XXXXXXXX PMINSW MM2, MM4", + "0fead4"), + (m32, "XXXXXXXX PMINSW MM2, MM5", + "0fead5"), + (m32, "XXXXXXXX PMINSW MM2, MM6", + "0fead6"), + (m32, "XXXXXXXX PMINSW MM2, MM7", + "0fead7"), + (m32, "XXXXXXXX PMINSW MM3, MM0", + "0fead8"), + (m32, "XXXXXXXX PMINSW MM3, MM1", + "0fead9"), + (m32, "XXXXXXXX PMINSW MM3, MM2", + "0feada"), + (m32, "XXXXXXXX PMINSW MM3, MM3", + "0feadb"), + (m32, "XXXXXXXX PMINSW MM3, MM4", + "0feadc"), + (m32, "XXXXXXXX PMINSW MM3, MM5", + "0feadd"), + (m32, "XXXXXXXX PMINSW MM3, MM6", + "0feade"), + (m32, "XXXXXXXX PMINSW MM3, MM7", + "0feadf"), + (m32, "XXXXXXXX PMINSW MM4, MM0", + "0feae0"), + (m32, "XXXXXXXX PMINSW MM4, MM1", + "0feae1"), + (m32, "XXXXXXXX PMINSW MM4, MM2", + "0feae2"), + (m32, "XXXXXXXX PMINSW MM4, MM3", + "0feae3"), + (m32, "XXXXXXXX PMINSW MM4, MM4", + "0feae4"), + (m32, "XXXXXXXX PMINSW MM4, MM5", + "0feae5"), + (m32, "XXXXXXXX PMINSW MM4, MM6", + "0feae6"), + (m32, "XXXXXXXX PMINSW MM4, MM7", + "0feae7"), + (m32, "XXXXXXXX PMINSW MM5, MM0", + "0feae8"), + (m32, "XXXXXXXX PMINSW MM5, MM1", + "0feae9"), + (m32, "XXXXXXXX PMINSW MM5, MM2", + "0feaea"), + (m32, "XXXXXXXX PMINSW MM5, MM3", + "0feaeb"), + (m32, "XXXXXXXX PMINSW MM5, MM4", + "0feaec"), + (m32, "XXXXXXXX PMINSW MM5, MM5", + "0feaed"), + (m32, "XXXXXXXX PMINSW MM5, MM6", + "0feaee"), + (m32, "XXXXXXXX PMINSW MM5, MM7", + "0feaef"), + (m32, "XXXXXXXX PMINSW MM6, MM0", + "0feaf0"), + (m32, "XXXXXXXX PMINSW MM6, MM1", + "0feaf1"), + (m32, "XXXXXXXX PMINSW MM6, MM2", + "0feaf2"), + (m32, "XXXXXXXX PMINSW MM6, MM3", + "0feaf3"), + (m32, "XXXXXXXX PMINSW MM6, MM4", + "0feaf4"), + (m32, "XXXXXXXX PMINSW MM6, MM5", + "0feaf5"), + (m32, "XXXXXXXX PMINSW MM6, MM6", + "0feaf6"), + (m32, "XXXXXXXX PMINSW MM6, MM7", + "0feaf7"), + (m32, "XXXXXXXX PMINSW MM7, MM0", + "0feaf8"), + (m32, "XXXXXXXX PMINSW MM7, MM1", + "0feaf9"), + (m32, "XXXXXXXX PMINSW MM7, MM2", + "0feafa"), + (m32, "XXXXXXXX PMINSW MM7, MM3", + "0feafb"), + (m32, "XXXXXXXX PMINSW MM7, MM4", + "0feafc"), + (m32, "XXXXXXXX PMINSW MM7, MM5", + "0feafd"), + (m32, "XXXXXXXX PMINSW MM7, MM6", + "0feafe"), + (m32, "XXXXXXXX PMINSW MM7, MM7", + "0feaff"), + + + + (m32, "00674296 MOVD ESI, MM1", + "0F7ECE"), + (m32, "00674293 MOVD MM1, EBX", + "0F6ECB"), (m32, "00000000 AAA", "37"), (m32, "00000000 AAS", @@ -1651,27 +2170,29 @@ reg_tests = [ (m32, "00000000 XORPS XMM1, XMM2", "0f57ca"), - (m32, "00000000 XORPS XMM1, DWORD PTR [EDI+0x42]", + (m32, "00000000 XORPS XMM1, XMMWORD PTR [EDI+0x42]", "0f574f42"), (m32, "00000000 XORPD XMM1, XMM2", "660f57ca"), - (m32, "00000000 MOVAPS DWORD PTR [EBP+0xFFFFFFB8], XMM0", + (m32, "00000000 MOVAPS XMMWORD PTR [EBP+0xFFFFFFB8], XMM0", "0f2945b8"), - (m32, "00000000 MOVAPS XMM0, DWORD PTR [EBP+0xFFFFFFB8]", + (m32, "00000000 MOVAPS XMM0, XMMWORD PTR [EBP+0xFFFFFFB8]", "0f2845b8"), - (m32, "00000000 MOVAPD WORD PTR [EBP+0xFFFFFFB8], XMM0", + (m32, "00000000 MOVAPD XMMWORD PTR [EBP+0xFFFFFFB8], XMM0", "660f2945b8"), - (m32, "00000000 MOVUPS XMM2, DWORD PTR [ECX]", + (m32, "00000000 MOVUPS XMM2, XMMWORD PTR [ECX]", "0f1011"), - (m32, "00000000 MOVSD XMM2, DWORD PTR [ECX]", + (m32, "00000000 MOVSD XMM2, QWORD PTR [ECX]", "f20f1011"), - (m32, "00000000 MOVSD DWORD PTR [EBP+0xFFFFFFD8], XMM0", + (m32, "00000000 MOVSD XMM2, XMM1", + "f20f10d1"), + (m32, "00000000 MOVSD QWORD PTR [EBP+0xFFFFFFD8], XMM0", "f20f1145d8"), (m32, "00000000 MOVSS XMM2, DWORD PTR [ECX]", "f30f1011"), - (m32, "00000000 MOVUPD XMM2, DWORD PTR [ECX]", + (m32, "00000000 MOVUPD XMM2, XMMWORD PTR [ECX]", "660f1011"), (m32, "00000000 MOVSS DWORD PTR [EBP+0xFFFFFC00], XMM0", @@ -1682,32 +2203,42 @@ reg_tests = [ (m32, "00000000 ADDSS XMM2, DWORD PTR [ECX]", "f30f5811"), - (m32, "00000000 ADDSD XMM2, DWORD PTR [ECX]", + (m32, "00000000 ADDSS XMM1, XMM2", + "f30f58ca"), + (m32, "00000000 ADDSD XMM2, QWORD PTR [ECX]", "f20f5811"), - (m32, "00000000 ADDPS XMM2, DWORD PTR [ECX]", + (m32, "00000000 ADDSD XMM2, XMM1", + "f20f58d1"), + (m32, "00000000 ADDPS XMM2, XMMWORD PTR [ECX]", "0f5811"), - (m32, "00000000 ADDPD XMM2, DWORD PTR [ECX]", + (m32, "00000000 ADDPD XMM2, XMMWORD PTR [ECX]", "660f5811"), - (m32, "00000000 MULSD XMM2, DWORD PTR [ECX]", + (m32, "00000000 MULSD XMM2, QWORD PTR [ECX]", "f20f5911"), (m32, "00000000 PXOR XMM0, XMM0", "0fefc0"), - (m32, "00000000 UCOMISD XMM0, DWORD PTR [EBP+0xFFFFFFD8]", + (m32, "00000000 UCOMISD XMM0, QWORD PTR [EBP+0xFFFFFFD8]", "660f2e45d8"), - (m32, "00000000 ANDPD XMM0, DWORD PTR [EBX+0x2CBD27]", + (m32, "00000000 ANDPS XMM0, XMMWORD PTR [EBX+0x2CBD27]", + "0f548327bd2c00"), + (m32, "00000000 ANDPD XMM0, XMMWORD PTR [EBX+0x2CBD27]", "660f548327bd2c00"), (m32, "00000000 SUBSD XMM1, XMM0", "f20f5cc8"), - (m32, "00000000 MAXSD XMM0, DWORD PTR [EBX+0x2CBD37]", + (m32, "00000000 MAXSD XMM0, QWORD PTR [EBX+0x2CBD37]", "f20f5f8337bd2c00"), + (m32, "00000000 MAXSS XMM0, DWORD PTR [EBX+0x2CBD37]", + "f30f5f8337bd2c00"), (m32, "00000000 CVTSI2SD XMM0, EBX", "f20f2ac3"), + (m32, "00000000 CVTSI2SS XMM0, EBX", + "f30f2ac3"), (m32, "00000000 PMINSW MM0, MM1", "0feac1"), @@ -1770,9 +2301,16 @@ reg_tests = [ (m64, "00000000 MOVD DWORD PTR [RAX+R10*0x8], XMM4", "66420f7e24d0"), - (m64, "00000000 MOVQ XMM4, DWORD PTR [RAX+R10*0x8]", + (m32, "00000002 MOVQ XMM4, QWORD PTR [EAX+EDX*0x8]", + "F30F7E24D0"), + (m32, "00000008 MOVQ QWORD PTR [EAX+EDX*0x8], XMM4", + "660FD624D0"), + (m32, "0000000E MOVQ QWORD PTR [EAX+EDX*0x8], MM4", + "0F7F24D0"), + + (m64, "00000000 MOVQ XMM4, QWORD PTR [RAX+R10*0x8]", "f3420f7e24d0"), - (m64, "00000000 MOVQ XMM1, DWORD PTR [R12+0xFFFFFFFFFFFFFFE0]", + (m64, "00000000 MOVQ XMM1, QWORD PTR [R12+0xFFFFFFFFFFFFFFE0]", "f3410f7e4c24e0"), @@ -1790,9 +2328,9 @@ reg_tests = [ (m32, "00000000 POR XMM0, XMM1", "660febc1"), - (m32, "00000000 MOVDQU XMM1, DWORD PTR [ESI]", + (m32, "00000000 MOVDQU XMM1, XMMWORD PTR [ESI]", "f30f6f0e"), - (m32, "00000000 MOVDQA DWORD PTR [ESP], XMM0", + (m32, "00000000 MOVDQA XMMWORD PTR [ESP], XMM0", "660f7f0424"), (m32, "00000000 LES EDI, DWORD PTR [ESI]", @@ -1830,6 +2368,23 @@ reg_tests = [ (m32, "00000000 PADDQ XMM0, XMM1", "660fd4c1"), + (m32, "00000007 PADDB MM4, QWORD PTR [EAX+EDX*0x8]", + "0FFC24D0"), + (m32, "0000000B PADDB XMM4, XMMWORD PTR [EAX+EDX*0x8]", + "660FFC24D0"), + + (m32, "00000000 PADDB MM0, MM1", + "0ffcc1"), + (m64, "00000000 PADDB MM0, MM1", + "0ffcc1"), + (m32, "00000000 PADDW MM0, MM1", + "0ffdc1"), + (m32, "00000000 PADDD MM0, MM1", + "0ffec1"), + (m32, "00000000 PADDQ MM0, MM1", + "0fd4c1"), + + ## Substractions # SSE (m32, "00000000 PSUBB XMM0, XMM1", @@ -1890,6 +2445,12 @@ reg_tests = [ "f30f5ac0"), (m32, "00000000 CVTSS2SD XMM0, DWORD PTR [EBP+0xFFFFFFD0]", "f30f5a45d0"), + + (m32, "00000001 CVTSD2SS XMM4, QWORD PTR [EAX+EDX*0x8]", + "F20F5A24D0"), + (m32, "00000006 CVTSS2SD XMM4, DWORD PTR [EAX+EDX*0x8]", + "F30F5A24D0"), + ] diff --git a/test/test_all.py b/test/test_all.py index 7270af3d..2f4efc88 100644 --- a/test/test_all.py +++ b/test/test_all.py @@ -41,6 +41,7 @@ for script in ["x86/sem.py", "arm/arch.py", "arm/sem.py", "aarch64/unit/mn_ubfm.py", + "aarch64/arch.py", "msp430/arch.py", "msp430/sem.py", "sh4/arch.py", |