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-rw-r--r--miasm2/arch/x86/arch.py1
-rw-r--r--test/arch/x86/arch.py3
2 files changed, 3 insertions, 1 deletions
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index 0637d3e9..bf25a5df 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -3759,6 +3759,7 @@ addop("prefetch0", [bs8(0x0f), bs8(0x18)] + rmmod(d1, rm_arg_m08))
 addop("prefetch1", [bs8(0x0f), bs8(0x18)] + rmmod(d2, rm_arg_m08))
 addop("prefetch2", [bs8(0x0f), bs8(0x18)] + rmmod(d3, rm_arg_m08))
 addop("prefetchnta", [bs8(0x0f), bs8(0x18)] + rmmod(d0, rm_arg_m08))
+addop("prefetchw", [bs8(0x0f), bs8(0x0d)] + rmmod(d1, rm_arg_m08))
 
 addop("pushw", [bs8(0xff), stk, bs_opmode16] + rmmod(d6))
 addop("pushw", [bs("01010"), stk, reg, bs_opmode16])
diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py
index d48a707c..29df049d 100644
--- a/test/arch/x86/arch.py
+++ b/test/arch/x86/arch.py
@@ -1744,7 +1744,8 @@ reg_tests = [
      "0f1818"),
     (m32, "00000000    PREFETCHNTA BYTE PTR [EAX]",
      "0f1800"),
-
+    (m64, "00000000    PREFETCHW  BYTE PTR [RDI]",
+     "0f0d0f"),
 
     (m16, "00000000    PUSHW      AX",
      "50"),