diff options
| -rw-r--r-- | miasm2/arch/x86/sem.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 939cd400..b8317ea7 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -735,9 +735,9 @@ def _shift_tpl(op, ir, instr, a, b, c=None, op_inv=None, left=False, # An overflow can occured, emulate the 'undefined behavior' # Overflow behavior if (shift / size % 2) - base_cond_overflow = c if left else ( - c - m2_expr.ExprInt(1, size=c.size)) - cond_overflow = base_cond_overflow & m2_expr.ExprInt(a.size, c.size) + base_cond_overflow = shifter if left else ( + shifter - m2_expr.ExprInt(1, size=shifter.size)) + cond_overflow = base_cond_overflow & m2_expr.ExprInt(a.size, shifter.size) if left: # Overflow occurs one round before right mask = m2_expr.ExprCond(cond_overflow, mask, ~mask) @@ -750,7 +750,7 @@ def _shift_tpl(op, ir, instr, a, b, c=None, op_inv=None, left=False, # Overflow case: cf come from src (bit number shifter % size) cf_from_src = m2_expr.ExprOp(op, b, - (c.zeroExtend(b.size) & + (shifter.zeroExtend(b.size) & m2_expr.ExprInt(a.size - 1, b.size)) - i1) cf_from_src = cf_from_src.msb() if left else cf_from_src[:1] new_cf = m2_expr.ExprCond(cond_overflow, cf_from_src, cf_from_dst) |